General Electric Company

Richard D Baertsch

William E Engeler

Jerome Johnson Tiemann

Nick Andrew Van Stralen

Robert Gideon Wodnicki

Daniel Arthur Staver

Walter Vincent Dixon, Iii

Dale M Brown

John Eric Tkaczyk

Scott Charles Evans

Scott William Petrick

David Byrd Ribner

Manjin J Kim

Thomas L Vogelsong

Marvin Garfinkel

Lawrence Richard Skrenes

Howard S Goldberg

Douglas E Sease

A detector framing node controls generation of radiation and radioscopic image detection Radioscopic image data is acquired and communicated independently of a host computer operating system. The detector framing node controls events in real time according to an event instruction sequence and receives the image data by way of an image detection interface into a memory unit. The image data is output from the memory unit to host memory of the host computer through a computer communication interface and under the control of a control unit. The detector framing node selects a flat panel detector from a plurality of different flat panel detectors and the image data is selectively reordered according to parameters of the selected flat panel detector before communication to host memory.

Detector framing node architecture to communicate image data

An imaging system includes a programmable detector framing node controlling generation of radiation and controlling radioscopic image detection. Radioscopic image data is acquired by the detector framing node and communicated to a host memory of a host computer independently of a host computer operating system. Image data is received from a flat panel detector and is selectively reordered according to parameters of the selected flat panel detector before communication to the host memory. The detector framing node includes an image detection interface to receive the image data and a control unit to select a predetermined portion of the image data for storage into a detector memory unit before communication to the host memory.

Communication of image data from image detector to host computer

A system for communicating with a residential electrical load center, including a residential electrical wiring system and at least one electronic communicating circuit breaker. The electronic communicating circuit breaker includes a fuse protected communications and control module. The system provides power to the fuse protected communications and control module utilizing the residential electrical wiring system, and operates the electronic communicating circuit breaker utilizing the fuse protected communications and control module regardless of whether the electronic communicating circuit breaker is in an 'Open' or 'Closed' state.

Electronic communicating residential circuit breaker

A current transformer for a ground fault circuit breaker used on a circuit having at least one line conductor and a neutral conductor includes a toroidal core having a circular opening defining a center point and a multi-turn winding wound on the core. A first guide member is disposed on one side of the core, and a second guide member is disposed on another side of the core. The first and second guide members each have a hole for receiving the line conductor and a hole for receiving the neutral conductor formed therein. The guide members thus position the conductors with respect to the core. The present invention also includes a method of correcting asymmetries in the current transformer. The method includes measuring the magnitude and orientation of any asymmetries, and then altering the current transformer based on the measured magnitude and orientation of the asymmetries so as to eliminate the asymmetries.

Current transformer and method for correcting asymmetries therein

The fail-safe electronic circuit breaker includes a test circuit connected to a fault detection circuit. The test circuit selectively generates a simulated circuit fault that is supplied to the fault detection circuit. The fail-safe electronic circuit breaker also includes a trip mechanism disabler that is connected to the test circuit. The trip mechanism disabler permanently disables the fail-safe electronic circuit breaker when the fault detection circuit fails to detect the simulated circuit fault after about a predetermined amount of time.

Fail-safe electronic circuit breaker

A real time data acquisition system includes a personal computer and a detector framing node cooperating to control generation of radiation and control radiographic detection. Data is acquired by a detector framing node and communicated independently of a non-real time operating system running on a host computer. The detector framing node controls events in real time according to an event instruction sequence and communicates received radioscopic data to a host memory. Data is received from a selected flat panel detector of a plurality of different flat panel detectors. The data is received as single frames or continuous frames before communication to the host memory.

Real time data acquisition system including decoupled host computer

A ground fault circuit breaker for use on a circuit having at least one line conductor and a neutral conductor includes a first transformer having a first toroidal core and a second transformer having a second toroidal core. The first and second cores are arranged concentrically with one another on a printed circuit board, which is disposed with a compact circuit breaker housing. The line and neutral conductors pass through both transformer cores.

Ground fault circuit breaker

A signal processing circuit can be used to select between a high bias current and good noise performance or a low bias current and poorer noise performance. The circuit comprises an input device having high impedance and low noise characteristics. A first current source provides a minimal current level through the input device. Additional current sources provide additional current through the input device to improve noise performance of the circuit. The additional current sources can be switched into the circuit when improved noise performance is required, and switched out of the circuit to conserve power when improved noise performance is not required.

Means of selecting low noise performance or low power dissipation in the analog front end of a custom integrated circuit

A current transformer for a ground fault circuit breaker used on a circuit having at least one line conductor and a neutral conductor includes a toroidal core having a circular opening defining a center point and a multi-turn winding wound on the core. A first guide member is disposed on one side of the core, and a second guide member is disposed on another side of the core. The first and second guide members each have a hole for receiving the line conductor and a hole for receiving the neutral conductor formed therein. The guide members thus position the conductors with respect to the core. Also included is a method of correcting asymmetries in the current transformer. The method includes measuring the magnitude and orientation of any asymmetries, and then altering the current transformer based on the measured magnitude and orientation of the asymmetries so as to eliminate the asymmetries.

An improved high order interpolative oversampled (sigma delta) analog-to-digital converter network including a plurality of cascade-coupled integrator stages is formed on a single integrated circuit chip in a manner that conserves power and chip area. Each integrator stage includes a differential amplifier, at least one input capacitor and at least one feedback capacitor. The power dissipation and occupied chip area are minimized by down-sizing the chip area occupied by the capacitors and differential amplifiers (op amps) in all but the first integrator stage. The high gain of the first integrator stage makes the noise contribution of subsequent integrator stages negligible so that the higher noise of the subsequent integrator stages is tolerable.

High order sigma delta oversampled analog-to-digital converter

A capacitor structure which is particularly suitable for use in analog integrated circuit devices employs an intermediate layer of a refractory metal disposed in a thin layer overlying a flat dielectric surface. The thinness and the low reflectivity of the refractory metal facilitates precise patterning of the upper plate of the capacitor structure. In the present invention, capacitance is no longer determined by imprecise cuts through thick oxide layers or by patterning of thick metallization layers within these apertures. The use of refractory metals in the capacitor structure also readily permits the incorporation of resistive circuit elements.

Refractory metal capacitor structures, particularly for analog

A plurality of charge storage cells, each including first and second storage regions and corresponding first and second electrodes insulatingly overlying the storage regions are provided in a semiconductor substrate. Means are provided for introducing into each of the first charge storage regions a respective quantity of charge proportional to a respective sample of an analog signal. Means are provided for developing a plurality of voltage waveforms, each of the waveforms including a series of periods, and each period constituted of first and second subperiods. Means are provided for applying each of the voltage waveforms to a respective one of the second electrodes of the cells. A high absolute level of a waveform applied to a second electrode of a cell causing charge in the first storage region thereof to transfer to the second storage region thereof and a low absolute level of the waveform applied to a second electrode of a cell causing charge in the second storage region thereof to transfer to the first storage region thereof. Each of the waveforms has a low absolute level during a first subperiod and an absolute level which is either high or low during a second subperiod in response to a respective reference signal, whereby charge in each cell is transferred between the first and second charge storage regions thereof in a time sequence determined by a respective reference signal. Means are provided connected in circuit with the first storage electrodes for sensing the total net charge transferred to and from the first charge storage regions during a common period of the voltage waveforms.

Surface charge signal processing apparatus

A charge transfer device is described for the conversion of a sequence of samples of a signal occurring at high frequency into simultaneous data samples occurring at a substantially lower frequency and substantially longer duration.

Charge transfer serial-to-parallel converter

A charge transfer shift register is described in which a first section is operated at a first clock frequency, a second section is operated at a second clock frequency, and an intermediate section located between the first and second sections is operated at fixed potential.

Charge transfer dual frequency delay line with phase independent coupling

A conductor-insulator-semiconductor (CIS) structure for a random access surface charge memory system is disclosed. The memory system comprises an array of memory cells including charge storage regions, charge transfer regions and charge receive-source regions formed along the surface-adjacent portions of a semiconductor substrate. A charge-storage line insulatingly overlies the storage regions of a row of memory cells and a bit line, comprising an extended region of opposite-conductivity-type, interconnects the receive-source regions of the same memory cells. Addressing in the Y-direction (word selection) is provided by charge transfer lines insulatingly overlying the charge transfer regions of a column of memory cells. Selected memory cells are addressed for read and write purposes by first activating the word select line which makes available one cell in each row of the memory. The desired row is then selected by means external to the array of memory cells. All cells of the selected word line are refreshed, but only one cell is addressed for read and write purposes. Means for reading, writing and refreshing data in the memory system are also disclosed.

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Scotia, NY, United States of America

Richard D Baertsch