Neonet Lllc

Neonet LLC

Richard Conlin

Peter Marconi

Tim Wright

Mukesh Chatter

Zbigniew Opalka

Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like

A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.

Growing community of inventors

Franklin, MA, United States of America

Richard Conlin