Tilera Corporation

Richard Conlin

Mark B Rosenbluth

Anant Agarwal

Carl Ramey

Matthew Mattina

David M Wentzlaff

Ian Rudolf Bratt

Christopher J Jackson

Bruce Edwards

Richard Schooler

Christopher D Metcalf

Liewei Bao

Chyi-Chang Miao

Patrick Robert Griffin

Kenneth M Steele

Shane Bell

John A Amann

Mathew Hostetter

Ben Harrison

Kevin Joyce

Christine Deignan

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Method and system for routing scan chains in an array of processor resources

Growing community of inventors

Groton, MA, United States of America

Richard Conlin