International Business Machines Corporation

Richard Clyde Beckman

John C Sinibaldi

Lawrence P Andrews

Joseph C Petty, Jr

Gary L Turbeville

Robert Chih-Tsin Eng

Judith Marie Linger

Kevin Bradley Williams

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Apparatus including a host processor and communications adapters interconnected with a bus

The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Multi-speed DSP kernel and clock mechanism

Apparatus including a host processor and communications adapters

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Boca Raton, FL, United States of America

Richard Clyde Beckman