International Business Machines Corporation

Richard Charles Paddock

Donald W Price

Darwin W Norton, Jr

William F Detschel

Arthur Wilbert Holmes, Jr

Price Ward Oman

Gerald Bernard Long

Shing Chou Pi

An adapter for attachment to the bus or video display of a personal computer, workstation or like devices to a high performance parallel interface (HIPPI)channel of a host computer. In a system having at least three devices to be connected to a high performance parallel interface in a 'Daisy chain,' each of the devices has an adapter capable of both sending and receiving bursts of data with a data click. Each adapter includes an inbound receiver connected to the channel for receiving bursts of data and data clock and a decoder for decoding routing information contained in the bursts of data. A pass through logic circuit is connected to the decoder for interpreting the routing information. A first latch is connected to the inbound receiver for temporarily storing data bursts. A second latch is connected to the first latch for accepting data bursts when the routing information identifies a device to which the adapter is connected. A data selector is connected to the first latch for selecting data from the device or from the first latch. An outbound transmitter is connected to the channel for transmitting bursts of data and a data clock, the outbound transmitter also being connected to the data selector for transmitting data bursts to the next adapter in the Daisy chain from the first latch when the routing information does not identify the device.

High performance channel adapter having a pass through function

Adapters attach the bus or video display of a personal computer or workstation to a high performance parallel interface (HIPPI) channel of a host computer. The HIPPI channel operates at a burst rate of 100 megabytes (MB) per second. The adapter includes an electrical circuit interface to provide compatible signal levels between the HIPPI channel and the bus of the personal computer or workstation. The adapter attaching the bus includes a first-in, first-out (FIFO) buffer that receives data words from the HIPPI channel. Control logic monitors the status of the FIFO buffer and interlocks the operation of the personal computer or workstation bus with the HIPPI channel so that proper data transfer is performed by the FIFO buffer. The adapter attaching the video display includes a pair of buffers operating in a ping-pong fashion to allow data to be written while data is being read. The buffers can be addressed by the personal computer or workstation as if they were internal memory. To allow a plurality of workstations to be connected to a single HIPPI channel, the HIPPI adapter is modified to include a pass through function allowing the devices to be connected in a 'Daisy chain'.

Personal computer bus and video adapter for high performance parallel

A self-sequenced read only memory is shown wherein each word line contains dynamic logic circuits for energizing a next word line after the fixed time delay provided by the dynamic logic circuits. Self-sequencing inverters are physically placed within the array area thereby increasing reliability and reducing circuit wiring. When used as a microprogram control storage, the memory is divided into a plurality of self-sequenced control routines. When a certain function is to be performed, the first word line of the control routine for performing the selected function is energized. Since each word line includes a one cycle delay and is wired to the next sequential word line, no separate timing or address control is required to address word lines within a selected control routine. Once a control routine is energized, sequential microinstructions will be automatically fetched including branch and branch-on condition instructions. Branch operations can be implemented by connecting one of the outputs of the array to the branched-to word line. Branch-on condition can be implemented by gating the inverter in the branched-to instruction with an AND circuit. By virtue of the self-sequencing of the memory, branched-to word lines can be sequentially accessing memory words simultaneously with sequential memory word fetch operations within the branched from control routine. The branched-to control routine thereby acts as a modifier routine to modify the bit patterns of the memory words which continue to be fetched by the branched-from control routine.

Self-sequencing memory

A processor including a plurality of synchronized subprocessors, each implemented on an integrated circuit substrate and each having an instruction register and instruction executing circuits for independently executing a portion of the functions required by an instruction being simultaneously executed by each subprocessor. Execution is initiated and synchronized by simultaneously loading the same instruction into each subprocessor.

Distributed execution processor

Dynamic logic counting circuits are disclosed using recirculating latched memory stages having parallel shift circuits operating in synchronism with the latch circuits to control stepping of the counts. An alternate embodiment employs steering circuit controlled subcounters, each subcounter having a parallel shift circuit operating in synchronism with its respective subcounter to step the next succeeding subcounter when its respective subcounter reaches a predetermined count such as 9 for a binary coded decimal counter or 15 for a binary counter.

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Kingston, NY, United States of America

Richard Charles Paddock