Cirrus Logic Inc.

Richard Charles Owen

Karl Scott Mills

Mark Emil Bonnelycke

Jeffrey Michael Holmes

Bradley A May

Lauren Emory Linstad

Vernon Dennis Hasz

Sherwood Brannon

Mark Emill Bonnelycke

The present invention discloses methods and apparatus for implementing automatic graphics operations with selectable triggering mechanism. One mechanism is hardware related, using the vertical counter in the video control section of the graphics processor. The other mechanism is software related, using the host to directly command the graphics processor. The graphics operations are specified in the header file written by the host in the frame buffer memory. Several header files can be chained together to form a sequence of header files corresponding to very complex graphics operations. Automatic graphics operations, therefore, can be completed without further host intervention resulting in powerful graphics, video, and animation performance.

Integrated graphics processor having a block transfer engine for

A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.

Method and apparatus for executing a raster operation in a graphics

A method and apparatus for determining representative values for the chrominance components to be associated with a plurality of luminance components in a horizontally shrunken or stretched image for graphics controllers wherein display image data is stored in a buffer memory in a form associating a single set of U and V chrominance components with a plurality of Y luminance values. For a four to one shrinkage of an image in a format associating one set of chrominance components with four pixel luminance values wherein each pixel luminance value in the shrunken image initially has as associated set of chrominance components U.sub.0, U.sub.1, U.sub.2 and U.sub.3 and V.sub.0, V.sub.1, V.sub.2 and V.sub.3, the multiple values of the chrominance components are sequentially accumulated in a 3/4:1/4 ratio in such a manner as to provide an approximate average value for U and V for each set of four pixel luminance values in the shrunken image. Circuitry for processing the chrominance components making use of interpolation circuitry already used for interpolation between pixels for a stretched image is disclosed.

Method and apparatus for determining representative chrominance

A graphics controller circuit for converting a plurality of monochrome pixel data into a corresponding set of color pixel data in RGB 888 format. The graphics controller circuit packs the converted color pixel data into a plurality of 64-bit color pixel words, with each color pixel word comprising two complete color pixel words and portion of at least one another color pixel word. By having color pixel data cross word boundaries, graphics controller of the present invention optimally stores color pixel data in color pixel words. The graphics controller circuit further includes a half-word addressable split-RAM which enables continuous availability of subsets of monochrome pixel data during each clock cycle for conversion to color data.

Method and apparatus for converting monochrome pixel data to color pixel

A method and apparatus for improving pixel data write operations to a tile-based frame buffer. The present invention includes a byte enable first-in first-out register for storing byte enable data for masking pixel data writes to a tile based frame buffer when the pixel data crosses a tile boundary. Pixel data generated by a graphics processor to the frame buffer may traverse multiple tiles. With each 64-bits of pixel data generated, a corresponding byte of byte enable data is generated as mask data for the frame buffer. The byte enable circuit of the present invention may be implemented as a circular shift register to allow the byte enable data to be shifted, rather than being 'popped' after the pixel data has been written to the frame buffer. By shifting data rather than 'popping' data, the byte enable circuit is able to retain portions of the byte enable data to enable a correct write of a pixel word which may traverse tile boundaries.

Method and apparatus for optimizing pixel data write operations to a

A transaction queue for transferring data between a host bus and an internal system bus within a graphics controller is disclosed. The queue comprises a First In First Out (FIFO) memory having independent clocks for reading and writing. The queue accommodates address information, data, command information, byte enable information, decode information, and a tag. The tag is a 2 bit field used to identify the queued entries as address, last data, and burst data. In a preferred embodiment, single transactions are written to the queue with no wait states. In the case of an address entry, the address associated with the transaction is stored in the queue along with the command and decode information. A tag is also included that identifies the entry as an address. In the case of a final data entry, the data is stored in the next entry along with the byte enable information and a tag to indicate it is the last data of the transaction. In the case of a burst, the address entry is followed by multiple data entries that are each tagged as burst data. The final data entry of the burst will be tagged as the last data of the transaction in the same way as the data of a single transaction.

Transaction queue in a graphics controller chip

A method and apparatus to stretch video images in a graphics controller chip of a computer system. The graphics controller chip fetches four pixel data comprising two pixel data each from a first scan line and a second scan line of a source video image, and generates a set of additional pixels in a rectangular area defined by the four pixels. The graphics controller chip stores the pixels of rectangular portions in a display memory, and displays the pixel data of the stretched video image in a scan line order.

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Seattle, WA, United States of America

Richard Charles Owen