Pmc-sierra, Inc.

Richard Cam

Winston K Mok

Charles Kevin Huscroft

Steven F Lang

David Walden Wong

James Robert Hamstra

Jonathan David Loewen

A method of interfacing for packet and cell transfer between a first layer device and a second layer device, which includes dividing control information into an in-band portion and an out-of-band portion, transmitting the in-band portion in the data path, and transmitting the out-of-band portion outside of the data path.

System interface for cell and/or packet transfer

A method of reducing error-multiplication due to error events in a cell stream transmitted as a plurality of cell sub-streams which includes the steps of receiving an incoming cell stream in the form of an ordered sequence of cells including payload cells, transmitting the incoming cell stream in a round robin fashion on a plurality of physical links such that the ordered sequence of cells is transmitted as a plurality of cell sub-streams, with each cell sub-stream having a multiplexed set of cells from the incoming cell stream, and inserting stuff (st) cells into the cell sub-streams so as to form continuous streams of data. Sequence number cells which are inserted periodically into each cell sub-stream, are used to align the cell sub-streams in frames. Sets of cell location information for the cell sub-streams are encoded and contain the location of payload cells and st cells located within a corresponding cell sub-stream. The sets of cell location information are passed on to a receiving end where they are re-constructed at the receiving end. A sequence of the ordered sequence of cells from the cell sub-streams is re-constructed including decoding the sets of cell location information to identify and locate errored cells and missing cells within the cell sub-streams and demultiplexing and releasing error-free payload cells from the cell sub-streams.

ATM inverse multiplexing system

This document discloses some technical details of a FIFO interface used for both cell and packet data transfer. This interface is suitable for a large number of ports. It operates at an overall throughput of 800 Mb/s for 16-bit wide data paths at 50 MHz, and 3.2 Gb/s for 32-bit wide data paths at 100 MHz. It is designed to have minimal compatibility issues with UTOPIA L2 and similar interfaces.

Bus interface for cell and/or packet data transfer

An ATM inverse multiplexing cell-based system for reducing error-multiplication due to error events in the transmitted cell stream, which includes a first IMA assembly having an input coupled to an incoming cell stream from a first ATM layer device, a second IMA assembly having an output coupled to a second ATM layer device, a plurality of links coupling the first IMA assembly to the second IMA assembly. The first IMA assembly includes a multiplexer for multiplexing the incoming cell stream onto the plurality of links and for inserting onto the links framing cells in the form of 'st' cells in place of idle cells and 'S' cells to mark divisions in each channel corresponding to a given number of cells or a given time interval between successive 'S' cells. An encoder encodes and inserts cell location information of both control cells and payload cells. The second IMA assembly includes a plurality of link buffers for receiving cells transmitted along respective ones of links. A demultiplexer demultiplexes cells by aligning 'S' cells on the link buffers and releasing payload cells for CDV smoothing. A decoder extracts and decodes location information from the framing cells to identify errored or missing cells and to mark the location of those cells. A discriminator distinguishes between errors in a header and errors in a payload of an errored cell and flushes all cells in the same frame on each link upon failure to identify an 'unknown' cell before encountering buffer overflow.

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Vancouver, Canada

Richard Cam