Altera Corporation

Richard C Saito

Perry Chun

Dominik J Schmidt

Y Eugene Chen

Adam J Wright

Jonathan C Park

Eugen Chen

Eugene Y Chen

Evgueni Ratchev

A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.

Method of creating a mask-programmed logic device from a pre-existing circuit design

An method of creating a physical layout of an integrated circuit. A schematic file () is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (). The method takes advantage of constraints on the schematic design to provide the layout file () quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

Algorithm and methodology for the polygonalization of sparse circuit schematics

An method of creating a physical layout of an integrated circuit. A schematic file ( ) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file ( ). The method takes advantage of constraints on the schematic design to provide the layout file ( ) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

A method of automatically generating a custom device layout includes the step of specifying a device type and an associated set of device parameters. The device type is then matched to a selected cell in a cell library. Physical layout regions of the selected cell are then selectively modified in accordance with the device parameters. The physical layout regions may also be selectively modified in accordance with technology design rules in a design rule library. The physical layout regions of the selected cell are then drawn.

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Sunnyvale, CA, United States of America

Richard C Saito