Texas Instruments Corporation

Richard C Meyer

Robert J Gove

Stephen Wesley Marshall

Donald B Doherty

Scott D Heimbuch

Jeffrey Brian Sampsell

Vishal Markandey

Austin L Huang

Harold E Bellis, Ii

Gerhard P Deffner

John R Reder

Carl W Davis

Gary L Sextro

Joseph G Egan

Joseph K Masters

Jefferey B Sampsell

A motor control system provides a low-cost method of phase-locking a motor to an input timing signal. Timer circuits 502, 506 measure the period of a timing signal and the relative phase between the timing signal and a motor rotor. A frequency command generator circuit 520 outputs a motor speed command based on the period of the timing signal and the relative phase of the timing signal compared to the motor rotor. The motor speed command controls the output of a motor driver circuit which drives the motor rotor speed synchronously with the input timing signal. The rotor speed is gradually altered to adjust the relative phase between the input timing signal and the motor rotor. This results in a small frequency-lock error being used to maintain a predetermined phase relationship between the timing signal and the motor rotor.

Low-cost phase-lock motor control method and architecture

A method and structure for a display system having multiple spatial light modulators (SLMs) (16), each of which contributes an image of one color that is perceived by the viewer as a combined image. The SLMs (16) have more rows and columns of pixel elements (42) than rows or columns of pixel data to be displayed. A window of 'active' pixel elements (42) can be shifted up and down or right and left by selecting which pixel elements (42) are to receive data. The addressing circuit (31, 31a, 35, 35a) of each SLM 16 can be controlled so as to accomplish this shifting.

Alignment for display having multiple spatial light modulators

A method of adjusting color temperature of images displayed by a display system (10) whose images are based on sequential pixel data and are filtered with a color wheel (15, 15', 15'). The relative display times for each color are adjusted to result in a corresponding adjustment of color temperature. In a first embodiment (FIG. 2), the size of the color wheel's segments are changed as well as the display times for data corresponding to each segment. In a second embodiment (FIG. 3), the display times for data corresponding to one or more segments are decreased with a black display time to fill in the difference.

Color temperature compensation for digital display system with color

A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.

Color phase control for projection display using spatial light modulator

A graphics data unit (17) for a digital television receiver (10) that uses a spatial light modulator (16). The graphics data unit (17) has a graphics processor (22), which offloads graphics processing tasks, such as for closed captioning and on-screen display, from a main processor (14). The graphics data unit (17) also has a character memory (24), which stores fonts for closed caption and on-screen display characters. A read-only memory (22a) stores graphics primitives. The character fonts and the graphics primitives may be adapted to compensate for staggered pixel layouts of the spatial light modulator (16).

Jagged edge compensator for staggered pixel layouts of a spatial light

A digital television system (10) is provided. System (10) may receive a video signal at composite video interface and separation circuit (16). The video signal is separated into separate video signals by composite video interface and separation circuit (16). The separate video signals are converted to digital video signals in analog to digital converter circuit (18). Line slicer (14) divides each line of digital video signal into a plurality of channels such that each channel may be processed in parallel by channel signal processors (22a) through (22d). Each channel signal processor (22a) through (22d) may provide two lines of output for each line of video input. The processed digital video signals may be formatted for displays (26a) through (26c) in formatters (24a) through (24c).

Digital television system

A system (14') for processing pixel video data having a selectable number of bits is provided. The system (14') comprises first, second and third video processors (20), (22) and (24). The first video processor (20) receives and processes pixel data of a luminance video signal. The second video processor (22) may receive and process pixel data of a chrominance video signal and may generate one of first, second and third video signal outputs. The third video processor (24) may process the chrominance video signal and may also generate at least two of the output video signals.

System and method for processing video data

A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

System and method for packaging data into video processor

A film-to-video format detector (24) for a digital television receiver (10). The detector (24) receives pixel data from a current field and a second preceding field. It determines a set of pixel difference values, sums them to obtain a field difference value, and compares the field difference value to a threshold. These steps are repeated to obtain a series of field difference indicators. This series is analyzed to determine whether it has a pattern corresponding to a film-to-video format.

Growing community of inventors

Plano, TX, United States of America

Richard C Meyer