Xilinx, Inc.

Integrated Device Technology, Inc.

Richard C Li

Hy V Nguyen

Chau-Chin Wu

Ta-Ke Tien

James Karp

Scott S Nance

Abu K Eghan

Jennifer Wong

Patrick J Crotty

Qi Lin

Xin X Wu

James A Walstrum, Jr

Phillip A Young

Hassan K Bazargan

Mohammed Fakhruddin

Fu-Hing Ho

Mohammad R Tamjidi

A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (R) that initiates bipolar snapback in the MOSFET output driver at which an ESD event occurs. The value of Rdepends upon a composite distance from the centroid of each MOSFET output driver to the contact ring.

Shared electrostatic discharge protection for integrated circuit output drivers

An input/output ('I/O') circuit has a first N-channel metal-oxide semiconductor ('NMOS') field-effect transistor (&#x201c;FET&#x201d;) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (&#x201c;PMOS&#x201d;) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (&#x201c;LVDS&#x201d;) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.

Method and apparatus to reduce footprint of ESD protection within an integrated circuit

An integrated circuit device is described. In particular, the integrated circuit comprises a substrate comprising active devices; a plurality of metal layers formed over the substrate, the plurality of metal layers being separated by insulating layers; a plurality of vias enabling connections to the active devices of the substrate; a contact pad support structure defining an opening in a metal layer of the plurality of metal layers and being coupled to an interconnect line; and a contact pad formed over the contact pad support structure. A method of implementing a contact pad in an integrated circuit is also disclosed.

Integrated circuit and method of implementing a contact pad in an integrated circuit

An output circuit allows the slew rate of its output signal to be selectively adjusted. The output driver circuit includes an output driver and pre-driver circuits. The output driver includes an output transistor coupled between a first supply voltage and the output terminal. The pre-driver circuit selectively adjusts a series resistance between the output transistor's gate and a second supply voltage in response to mode control signals.

Slew rate control for output signals

A pad pattern of a die includes first and second sets of elongated pads. The first set of elongated pads is interleaved with the second set of elongated pads. Each of the elongated pads has a bond pad area and a probe pad. Each bond pad area has a first constant width along a substantial portion thereof. Similarly, each probe pad area has a second constant width along a substantial portion thereof. The first constant width is greater than the second constant width. Each elongated pad in the first set has a first orientation. Similarly, each elongated pad in the second set has a second orientation, opposite the first orientation.

Semiconductor die with high density offset-inline bond arrangement

An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path. The one-shot circuit then opens the third switch before the output pad fully discharges. Subsequently, the one-shot circuit returns to its stabilized state and closes the third switch, thereby connecting the substantially fully discharged output pad to ground through both the first and second paths.

Output driver with reduced ground bounce

A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.

Low voltage interface circuit with a high voltage tolerance

Problems associated with excessive crowbar current due to input signal transitions at a buffered programmable interconnect point are solved by inserting a transistor switch between power and ground. The inserted switch is in series with the input buffer and is controlled by a memory cell which also controls the pass/no-pass state of the interconnect. An OFF inserted switch blocks current that flows during switching when the memory cell output causes a no-pass state of the interconnect.

Programmable interconnect point having reduced crowbar current

A memory system having a single-sided memory cell, a first voltage supply terminal and a control circuit is provided. The single-sided memory cell has a first node and a second node. Data values are written to the memory cell by selectively applying data signals to the first node or the second node, and data values are read from the memory cell from the second node. The control circuit is coupled to receive a data signal having one of a first state and a second state. The control circuit couples the first node of the memory cell to the first voltage supply terminal when the data signal is in the first state, thereby writing a first data value to the memory cell. The control circuit couples the second node of the memory cell to the first voltage supply terminal when the data signal is in the second state, thereby writing a second data value to the memory cell. Because the first voltage supply terminal is used to write both the first and second data values to the memory cell, problems associated with inadequate write voltages are eliminated by appropriate selection of the first supply voltage.

Single-sided RAM cell and method of accessing same

A selectively decoupled latch circuit used for latching a signal. The circuit contains an input line for accepting an input signal to the circuit. A latch is connected to the input line for latching the input signal. A transfer gate is also connected to the input line and latch for transferring the input signal to the latch according to a clock signal. A transistor is connected in a series with a feedback loop associated with the latch. The transistor selectively decouples the feedback path according to the clock signal. By selectively decoupling the feedback path, it is easier for a new input signal to become latched because contention between a prior latched signal versus the new input signal is minimized. An output line is connected to the latch for outputting a latched signal.

Selectively decoupled I/O latch

An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ('ground bounce'). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

TTL input buffer with on-chip reference bias regulator and decoupling

In a sense amplifier, collectors of a first pair of transistors are connected to and drive the bases of a pair of output transistors, and the bases of the first pair of transistors and the emitters of the pair of output transistors are coupled to input nodes of the sense amplifier. The speed of the sense amplifier is enhanced over the prior art because changes in currents (or voltages) on the input nodes change both the emitter and base voltages of the pair of output transistors.

Growing community of inventors

Cupertino, CA, United States of America

Richard C Li