Advanced Micro Devices Corporation

Richard C Kittler

William Dow Heavlin

Ping Wen

Howard F Hsu

Kenneth J Mockler

Glenn S Warner

A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda. are optimized by minimizing a least squares difference between the observed repair rates and the model repair rates. The fabrication yield is computed as a predetermined function of the model repair rate including scale factor(s) for the circuit on the wafer being designed. The method can be used to select a redundancy scheme for the wafer by computing fabrication yields for a plurality of candidate redundancy schemes, and selecting the redundancy scheme which has the highest return for additional test, manufacturing and design investment.

Computer implemented method for estimating fabrication yield for

An improved method is provided for defining interconnect patterns in an integrated circuit fabricated on a semiconductor wafer. The improvement comprises the step of immersing the wafer in a weak base solution, prior to etching a titanium-tungsten barrier layer, so as to remove from the wafer chlorides and flourides remaining as a result of a previous step of etching a conductor layer. In a preferred embodiment of the invention, a step of immersing the wafer in a strong acid solution is also performed to remove chlorides from the wafer.

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Sunnyaale, CA, United States of America

Richard C Kittler