International Business Machines Corporation

Macronix International Co., Ltd.

Richard C Jordan

Daniel Francis Casper

Frank David Ferraiolo

Robert S Capowski

William C Laviola

Anthony J Perri

Peter R Tomaszewski

Hsiang-Lan Lung

Hsin-Yi Ho

Scott C Lewis

A memory configured to have data read therefrom is provided. The memory includes a data port including B transmitters disposed in parallel and for transferring data on both rising and falling edges of a clock, a first memory including a first data bus including N lines on which N bits can be transferred, and a second memory including a second data bus including N lines on which N bits can be transferred. The memory includes a data path controller including a data distributor disposed between the first and second memories and being connected to the data port, wherein, on the rising edge, the data distributor distributes a first data segment comprised of B bits from the first data bus to the data port and, on the falling edge, the data distributor distributes a second data segment comprised of B bits from the second data bus to the data port.

Phase change memory array architecture achieving high write/read speed

A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

Ring oscillator with adjustable delay

A digitally controlled oscillator includes an adjustable signal generating circuit adapted to generate an oscillation signal. A feedback loop receives the oscillation signal from the adjustable signal generating circuit. The feedback loop detects error in the oscillation signal and produces an error signal based on the error. The control logic circuit receives the error signal from the feedback loop and maintains the oscillation signal within a predetermined error range. Also, a state device that is connected to the adjustable signal generating circuit maintains a previous operating state of the adjustable signal generating circuit when the digitally controlled oscillator is temporarily powered down. When the digitally controlled oscillator is powered up after being temporarily powered down, the control logic starts the adjustable signal generating circuit at the previous operating state based upon data maintained within the state device, and restarts the feedback loop and error processing circuits in a way to avoid oscillator adjustments based on old data.

Digitally controlled oscillator with recovery from sleep mode

A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

Self timed interface

An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

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Lake Katrine, NY, United States of America

Richard C Jordan