Rockwell International Corporation

United States of America As Represented by the Secretary of the Air Force

Norton Company

Gigabit Logic

American Diversified Capital Corporation

Richard C Eden

Kenichi Nakano

Ira Deyhimy

James S Harris, Jr

Joseph T Longo

Edward R Gertner

John E Clarke

Austin M Andrews, Ii

Robert Miller

George R Kaelin

Alan S Fiedler

Frank S Lee

Earl S Cory

Fred W Scholl

John E Clark

Lucia O Bubulac

Timothy J Quilici

A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

Laminated diamond substrate

The disclosure is directed to an improved circuit and method which utilizes a plurality of generally planar diamond substrate layers. Electronic circuit elements are mounted on each of the substrate layers, and the substrate layers are disposed in a stack. Heat exchange means can be coupled generally at the edges of the substrate layers. In a disclosed embodiment, a multiplicity of generally planar diamond substrate layers and a multiplicity of generally planar spacer boards are provided. Each of the substrate layers has mounted thereon a multiplicity of electronic elements and conductive means for coupling between electronic elements. In general, at least some of the electronic elements on the substrate layers comprise integrated circuit chips. The substrate layers and spacer boards are stacked in alternating fashion so that spacer boards are interleaved between adjacent substrate layers. Each of the spacer boards has a multiplicity of electrical conductors extending through its planar thickness to effect coupling between electronic components on the substrate layers on its opposing sides. The extremely high thermal conductivity of diamond permits adequate heat removal from the defined three-dimensional circuit structure by heat exchange means that do not substantially interfere with electronic element density, with vertical interconnect density, or with the desire for small physical size.

Electronic circuit and method with thermal management

A V.sub.BB input threshold potential with feedback circuitry is used to stabilize all of the logic inputs on an GaAs IC to ECL compatible levels over a normal temperature range and normal power supply variations. The system called 'V.sub.BB -Feedback' uses 'zero translation delay' direct Capacitor Diode Fet Logic (CDFL) inputs. This is an extension of the CDFL circuit approach in which the voltage across the input level shift circuitry on all inputs is adjusted to maintain a threshold voltage equal to the dc potential on an 'extra' V.sub.BB input in spite of variations of temperature, power supply voltages or processing parameters such as MESFET pinchoff voltage. A dc potential (V.sub.BB) is applied to the 'extra' V.sub.BB input, which is an additional input that is essentially identical to the actual logic inputs. All of the logic input threshold voltages are then slaved to the V.sub.BB dc potential applied to the 'extra' V.sub.BB input. ECL compatability is accomplished by combining a reasonably compliant, but uniform, CDFL voltage shifter with feedback circuitry to maintain the shift voltages at proper levels thereby achieving the desired input logic threshold.

VBB-feedback threshold compensation

A data communication system for general purposes having a new ternary carrier frequency shift keying (TCSK) signal. The system is applied to a utility load control by transmission of a sub-carrier of an FM broadcast channel. It is decoded by a receiver, SCA decoder, TCSK filter and a two level or binary converter and used to communicate to a pre-programmed microprocessor which enables various load control functions to be performed. The general system also is given for a QPSK (quadraphase shift keying) operating system. A data transmission filter is split between the transmitter and receiver and is operated in cascade to give individual interference filtering at each end of the transmission while also providing combined action and wave shaping. A high accuracy FM decoder using zero crossing detection enables data recovery with simple circuits. A novel random time load restoration circuit for ramp-up is disclosed. A fail safe relay operator is also disclosed. The TCSK employs a novel 19 character hex code format which is 8 bit microprocessor compatible and directly usable for other purposes such as ASCII message transmission. Both QPSK and TCSK systems offer command structures of variable length so as to permit truncation of message and reduce total message transmit time.

Data communication system

A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write '1' and '0' lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write '1' line and the first level shifting diode. A second input isolation diode is connected between the write '0' line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode. An output isolation diode is connected between the drain of the output buffer FET and the output line.

Low power, high speed random access memory circuit

Disclosed is a logic circuit with a plurality of AND logic elements, each including a plurality of Schottky diodes with each cathode connected to a logic input and the anodes connected in common to establish an AND output. A diode pull up FET is provided for each AND output, with the source connected to the AND output, the gate connected to the source, and the drain connected to a source of positive bias potential. An OR logic element includes a plurality of Schottky diodes with each anode connected to one of the AND outputs and the cathodes connected in common to establish an OR output, while a diode pull down FET has its drain connected to the OR output, with the gate connected to the source and the source connected to a source of negative bias potential. A level shifting diode is placed between the OR output and the pull down FET. An output FET is connected through its gate to the drain of the diode pull down FET, with the source connected to ground and the drain providing a logic output from the circuit. An output pull up FET has its source connected to the drain of the output FET, the gate connected to the source, and the drain connected to the source of positive bias potential.

Schottky diode-diode field effect transistor logic

A logic circuit is provided which uses Schottky barrier switching diodes to perform the 'OR' logic function on logic inputs. The outputs from the switching diodes control the gate of a field-effect transistor (FET) which provides logic inversion and gain. The source of the FET is grounded and its drain provides the output of the logic circuit. Bias current for the switching diodes and gate turn-off current for the FET are provided by a pull down, and a pull up is provided to operate the FET. In a second embodiment, two separate groups of switching diodes control separate gates of a dual-gated FET to provide a two-level 'OR/NAND' logic circuit. In a third embodiment, the outputs from a pair of two-level logic circuits are joined to provide a three-level 'OR/NAND/WIRED-AND' logic circuit.

Schottky diode FET logic integrated circuit

A charge coupled device has a semi-insulating semiconductor for a substrate. Resistivity of the semiconductor is at least 10.sup.6 ohm cm. A semi-conductive layer is grown epitaxially or is implanted on the substrate to form a thin, active, charge transport layer. A row of parallel, closely spaced gates on the charge transport layer provides individual storage wells in the charge transport layer. In a preferred embodiment, ohmic contacts adjacent the first and last gates in the row of gates provide a means for injecting a signal into the charge transport layer and a means for detecting the signal. Preferably, the substrate is semi-insulating GaAs and the gates are Schottky barrier gates.

Buried channel charge coupled device with semi-insulating substrate

A narrow-band, inverted homo-heterojunction avalanche photodiode, configured in the shape of a mesa situated upon a substrate which is transparent to selected light energy wavelengths. The diode is inverted for operation such that the incoming light energy enters the substrate side, passes through a wavelength selective buffer layer and is absorbed upon entering the succeeding, active region. Avalanche gain is attained by drift from the area of absorption to the high field p-n homo-heterojunction located immediately thereafter. The device exhibits low levels of noise during operation because absorption is occurring in a low field region and because the ionization and breakdown noise associated with lattice mismatches is avoided through the formation of the p-n homo-heterojunction in one continuous growth process. Appropriate passivation of the mesa walls inhibits surface leakage and breakdown effects.

Method of making a narrow-band inverted homo-heterojunction avalanche

A high-speed, light emitting device which utilizes a solid state source for generating light for use in fiber optical communications. The source is an active, narrow band gap layer of semiconductive material between heterojunctions formed with a p.sup.+ -type material on one side of an n.sup.+ -type material on the other side. A mirror on the back of the source reflects light toward an optical fiber abutting the substrate on the front of the source. A side mirror traverses the edge of the active layer at an angle of about 45.degree. and reflects light traveling parallel to the active layer toward the optical fiber. Contacts are coupled to the semiconductor material for applying an electrical signal across the active layer to generate light. In a preferred embodiment, the active layer is GaAsSb joined to GaAlAsSb and the substrate is GaAs.

Light emitting device for optical communications

Narrow-band inverted homo-heterojunction avalanche photodiode

A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

Sensitive high speed solid state preamp

An inverted heterojunction photodiode for use as a laser detector sensitive to the 8 - 14 .mu.m portion of the infrared spectrum and operable above 77.degree. K. The diode structure comprises a PbTe substrate, a first buffer layer of a Pb.sub..90 Sn.sub..10 Te material on said substrate and a second active layer of a Pb.sub..80 Sn.sub..20 Te material on said buffer layer. The first and second layers are grown by liquid phase epitaxy.

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Thousand Oaks, CA, United States of America

Richard C Eden