Advanced Micro Devices Corporation

Spansion Llc.

Intel Corporation

Globalfoundies Inc.

Richard C Blish

Colin D Hatchard

J Courtney Black

Mohammad Massoodi

David E Lewis

Ian Morgan

Donald L Wollesen

Sunil Narayan Shabde

Frank Ruttenberg

Pramod D Patel

Sidharth

Robert E Likins

Paul Raymond Besser

Jun Zhai

Nicholas H Tripsas

Mehrdad Mahanpour

Glen P Gilfeather

Christy M-c Woo

Christine Hau-Riege

Michael David Fliesler

Bryan M Tracy

Timothy Z Hossain

Kurt Taylor

James L Hayward

Quang Nguyen

David C Greenlaw

Sharad M Shah

Daniel Yim

William D Smith

Jinsu Kwon

Bryan William Hancock

S Sidharth

Sidharth Sidharth

Jun “Charlie” Zhai

Devendra Natekar

Richard Dennis

Nicholas Brathwaite

Kok-Yong Yiang

John James Slevin

Scott E Johnson

An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound.

Soft error resistant circuitry

The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Copper interconnects with improved electromigration lifetime

A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.

Thermal interface material and semiconductor component including the thermal interface material

One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

Methods and systems for recovering data in a nonvolatile memory array

A plurality of channels are formed in a base, e.g., a substrate of an integrated circuit, each channel extending between edges of the base. Two pairs of manifolds are provided, the first pair communicating with a first group of channels and the second pair communicating with a second group of channels, the first group of channels and the first pair of plena isolated from the second group of channels and the second pair of plena. Each of the pairs of manifolds includes multiple branches coupled to the channels and a common plenum. Cooling fluid is injected into the channels from different sides of the base, causing fluid to flow in different directions in the two groups of channels, the channels in thermal contact with the integrated circuit.

Counterflow microchannel cooler for integrated circuits

An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.

Integrated circuit package and method

A lidded semiconductor device has a first layer applied to the lid, which first layer is chosen of a material which fluoresces upon application of non-visible electromagnetic waves thereto, for example, ultraviolet light. A second layer is provided over the first layer. Openings extend through the second layer and further extend to a substantial depth into the first layer, for example, generally halfway into the first layer, to expose portions of the first layer.

Prevention of counterfeit markings on semiconductor devices

In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.

Structure for minimizing hot spots in SOI device

The present neutron sensing device includes a first substantially planar array of flash memory cells, a second substantially planar array of flash memory cells having an edge adjacent an edge of the first substantially planar array of flash memory cells, and a third substantially planar array of flash memory cells having a first edge adjacent an edge adjacent an edge of the first substantially planar array of flash memory cells and a second edge adjacent an edge of the second substantially planar array of flash memory cells. The plane of the second substantially planar array of flash memory cells is at an angle relative to the plane of the first substantially planar array of flash memory cells, and the plane of the third substantially planar array of flash memory cells is at an angle relative to the plane of the first substantially planar array of flash memory cells, and is at an angle relative to the plane of the second substantially planar array of flash memory cells, in the preferred embodiment of all such angles being indicated as 90&#xb0;.

Neutron detecting device

Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliability

A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Method and system for removing conductive lines during deprocessing

Method for stepping identification and bond pad crater jeopardy identification in integrated circuits and apparatus which performs the method, A unique device, a polysilicon meander, is formed under each bond pad in the integrated circuit device. Connected to the meander is circuitry for determining the electrical, and hence mechanical, integrity of the meander. Failure of the meander by reason of microcrack formation in the several layers under the meander is detected by the high resistance of the meander. The circuitry will also resolve any potential mismatch between the actual mask revision of the integrated circuit and the corresponding revision of the test program.

Method and apparatus to achieve bond pad crater sensing and stepping identification in integrated circuit products

A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

Apparatus for metal stack thermal management in semiconductor devices

The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Method to improve chip scale package electrostatic discharge performance and suppress marking artifacts

A semiconductor structure is tested for latchup characteristics by imposing increasing levels of current thereon, and measuring increase in structure current in response thereto. When an imposition in current results in a corresponding increase in semiconductor structure current which is not substantially linearly proportional to the amount of current imposed thereon, onset of latchup is indicated. Other semiconductor structures are tested, and measurements are compared to gain knowledge of the structures tested.

Method for achieving synchronous non-destructive latchup characterization

Growing community of inventors

Saratoga, CA, United States of America

Richard C Blish