Hewlett-packard Development Company, L.P.

Richard Brabant

Jonathan Manuel Watts

Craig VanZante

A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.

Multi-process support in a shared register

A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.

Timeouts on accessing a shared resource

A generic interface for a module, method of providing a generic interface, and a module controller system providing a register slave having a generic interface are described. The interface includes an addressable interface, a control interface, and a module interface configured to interact with two or more module configurations. The interface has multiple operating modes at least one of which includes a monitor mode. The method includes receiving an address from a register master identifying the module address to be monitored, reading the received module address content from the module, and transmitting the read content to the monitor port. The system includes a register master, a register slave connected with the register master and adapted to connect with the module, and a monitor port connected with the register slave to receive the monitored module address contents. The register slave configured to interact with two or more module configurations and having a monitor mode for monitoring a specified module address.

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Roseville, CA, United States of America

Richard Brabant