General Instrument Corporation

Other

Richard B Rubinstein

Lamar T Baker

Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A 'virtual two-port' solution also is described for using single-port memory in the shared configuration with multiple address sources.

Shared, reconfigurable memory architectures for digital signal processing

A buffer amplifier for use with a ripple-carry binary generator comprises a pair of serially connected FET transistors. The input to one of the transistors is precharged by the preceding generator stage and also receives the ripple carry signal. A feedback loop from the output of the transistor to the input hastens the transition from the pre-charge condition to ground.

Buffer amplifier for ripple-carry binary generator

An integrated circuit ram amplifier includes a feedback loop which produces an output pulse before the output from the random access memory has completed its transition from full voltage to ground, thus increasing the computer's response time. The integrated circuit amplifier may find particular application in microprocessors (e.g. 8 bit word length, single bus two phase clock microprocessors).

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North Bergen, NJ, United States of America

Richard B Rubinstein