Motorola Corporation

Cyrix Corporation

National Semiconductor Corporation

Richard B Reis

Jesse R Wilson

John K Eitrheim

William D Atwell, Jr

R A Garibay, Jr

Mark W McDermott

Grady L Giles

James S Golab

Jeffrey S Byrne

Douglas Ewing Duschatko

Joseph Carbonaro

Lawrence H Hudepohl

Steve McMahan

Tai Dinh Ngo

A microprocessor is implemented using sense amplifiers to replace CMOS logic circuits, in order to provide low voltage, high frequency switching. The input node of the sense amplifier is maintained at a voltage just above or just below their trip-point of one inverter in order to obtain high-speed switching. Bench mark tests have shown that a microprocessor operating at 2.7 volts may obtain a frequency of 20 MHz and while the same microprocessor may operate at 5.5 volts and 40 MHz.

High speed processor for operation at reduced operating voltage

A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.

Method and apparatus for shifting data in an array of storage elements

An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Clock multiplication circuit and method

An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. The clock generator circuit includes a programmable delay stage having fixed and variable portions. The fixed portion preferably includes a series of logic elements of various types (NOR, NAND, NOT, pass gates, etc.), selected to match the worst case clock phase delay and which match speed variations as a function of voltage, temperature or processing conditions. The variable portion of the delay stage selects a propagation delay by way of programmable elements (e.g., mask programmable); multiplexers may be included therein to allow selection of the delay in a test mode. The high frequency clock is generated by a circuit having a set input receiving the input clock signal and a reset input receiving the output of the programmable delay stage; as a result, the output clock signal duty cycle depends upon the propagation delay through the programmable delay stage, and not upon the duty cycle of the input clock signal. A frequency divider may also be provided to generate a lower frequency clock based on the input clock signal. In addition, the set and reset circuits may be disabled in a non-clock doubling mode, in which another frequency divider may be enabled for generating an output clock signal.

Stable internal clock generation for an integrated circuit

A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal. This construction of the PLL circuit allows for the control signals to control the rate of change both for advancing and retarding the output clock frequency, and allows for on-chip implementation of the filter components in a manner compatible with MOS technology.

Integrated charge-pump phase-locked loop circuit

A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.

Sense amplifier with an integral logic function

A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.

Binary magnitude comparator with asynchronous compare operation and

A method and apparatus in an integrated circuit having a plurality of distinct circuit modules which eliminates undesired effects of clock skewing when a common system clock is used. The same phase of the same system clock is used by both a transmitting circuit module and a receiving circuit module when data is communicated between two circuit modules. The receiving circuit module has an input portion having a first transistor clocked by the same phase of the same system clock, a latch and a second transistor. The latch and second transistor are clocked by a complement of the same phase of the system clock.

Method and apparatus for eliminating clockskew race condition errors

An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor. A discharging n-channel transistor is connected in series between the parallel network and ground. The gate of the discharging transistor is coupled to the sense node. The sense amplifier can enter a power-saving disable mode, and entry is controlled by a sense amplifier enable signal. This mode has two possible states corresponding to the state of the sense amplifier immediately preceding disablement and enables the sense amplifier to avoid output glitches when leaving the disabled mode. The sense amplifier uses two negative feedback loops, including the charging and discharging n-channel transistors, to limit the swing on the sense node, and this swing is substantially independent of the number of parallel transistors that are conductive.

Growing community of inventors

Garland, TX, United States of America

Richard B Reis