Intel Corporation

Richard B O'Connor

Beeman C Strong

Michael W Chynoweth

Rajshree Chabukswar

Michael Mishaeli

Tsvika Kurts

Itamar S Kazachinsky

Anthony Wojciechowski

Vikas R Vasisht

Avner Lottem

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

Processor core power event tracing

A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.

Instruction and logic for interrupt and exception handling

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Irmo, SC, United States of America

Richard B O'Connor