Foveon, Inc.

National Semiconductor Corporation

Foveonics, Inc.

Richard B Merrill

Richard Francis Lyon

Richard M Turner

Kevin E Brehmer

Carver A Mead

Albert M Bergemont

Russel A Martin

Min-hwa Chi

Robert S Hannebauer

Milton B Dong

Glenn Jay Keller

Whu-Ming Young

Tsung-Wen Lee

Doug R Farrenkopf

Jaroslav Hynecek

Paul M Hubel

Samar K Saha

Douglas Robert Farrenkopf

Philip J Cacharelis

Kamesh V Gadepally

Shri Ramaswami

Timothy M Slagle

Peter J Manca

J Orion Pritchard

Edson D Gomersall

Enayet U Issaq

Kai Chen

Min-Hwa Chi

David C Reynolds

John M Pierce

Donald M Archer

Inderjit Singh

Edison Fong

James E Tornes

C S Teng

Mark O Bagula

Enayet O Issaq

James H Shibley

Rudolph J Guttosch

The invention describes in detail the structure of a CMOS image sensor pixel that senses color of impinging light without having absorbing filters placed on its surface. The color sensing is accomplished by having a vertical stack of three-charge detection nodes placed in the silicon bulk, which collect electrons depending on the depth of their generation. The small charge detection node capacitance and thus high sensitivity with low noise is achieved by using fully depleted, potential well forming, buried layers instead of undepleted junction electrodes. Two embodiments of contacting the buried layers without substantially increasing the node capacitances are presented.

Method and apparatus for improving sensitivity in vertical color CMOS image sensors

A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Pinned photodiode CMOS pixel sensor

An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.

CMOS pixel sensor with depleted photocollectors and a depleted common node

In a readout bus architecture having a first column, a readout means is coupled to a photodetector and configured to transfer charge from the photodetector. A select means is coupled to the photodetector and is configured to transfer charge from the photodetector. An address circuit is coupled to the first column through the select means and is configured to generate and decode an address and turn on the select means for the first column if the address matched the first column and if the address circuit received a corrected enable signal indicating that the first column is not defective. A correction circuit is coupled to the address circuit and is configured to generate the corrected enable signal indicating that the first column is not defective if the correction circuit determined that the first column is not defective.

Method and apparatus for eliminating image artifacts due to defective imager columns and rows

An array of multicolor CMOS pixel sensors has a plurality of photosensors per pixel, each photosensor coupled to a single sense node through a select transistor having a select input, each pixel sensor including a reset transistor coupled to the sense node and having a reset input, an amplifier coupled to the sense node and a row-select transistor coupled to the amplifier. The select inputs and the reset inputs for pixel sensors in a pair of adjacent rows are coupled to select signal lines and reset signal lines associated with the pair of rows. The amplifier transistors in individual columns of each row are coupled to a column output line through a row-select transistor having a row-select input. The row-select inputs for pixel sensors in each row of the array are coupled to a row-select line associated with the row.

Multi-color CMOS pixel sensor with shared row wiring and dual output lines

A pixel sensor comprises a first reset transistor having a drain coupled to a first potential, a gate coupled to a first reset line, and a source. A second reset transistor has a drain coupled to the first reset transistor source, a gate coupled to a second reset line, and a source coupled to a photodiode cathode. A source-follower transistor has a drain coupled to the first reset transistor source, a gate coupled to the photodiode cathode, and a source. A row-select transistor has a drain coupled to the source-follower transistor source, a gate coupled to a row-select signal line, and a source coupled to a column output line. An array of these pixel sensors further comprises timing and readout circuits that control the transistors in the pixel sensor to effect a reset operation that cancels the fixed pattern of threshold variations of the source-follower transistors.

Intra-pixel fixed-pattern-noise cancellation circuit and method

An active CMOS pixel sensor includes a red photodiode and a green photodiode coupled to sense nodes. Blue photodiodes are coupled to a blue sense node through select transistors. A blue reset transistor is coupled between a supply node and the blue sense node. A source-follower transistor is coupled to the blue sense node. A blue row-select transistor is coupled to the source-follower transistor and a biased blue column line. Red and green amplifier transistors have gates coupled to sense nodes, drains coupled to a supply node, and sources. Red and green reset transistors have drains coupled to the drains of the amplifier transistors, sources coupled to the sense nodes. Feedback capacitors couple the sense nodes to the reset transistor drains. Red and green row-select transistors have drains coupled to the sources of the amplifier transistors, sources coupled to biased column lines, and gates coupled to a red-green row-select line.

High-gain multicolor pixel sensor with reset noise cancellation

A method of manufacturing an imaging subsystem is provided. The method includes manufacturing an image sensing device including a unique identifier. The image sensing device is incorporated into an imaging subsystem. The imaging subsystem is operated and characterization parameters of the image sensing device operation are determined based thereon. The characterization parameters are associated with the unique identifier in a repository of characterization parameters that is separate from the imaging subsystem.

Methods for manufacturing and testing image sensing devices

An array of vertical color filter (VCF) sensor groups, optionally including or coupled to circuitry for converting photogenerated carriers produced in the sensors to electrical signals, and methods for reading out any embodiment of the array. The array has a top layer (including the top sensors of the sensor group) and at least one low layer including other ones of the sensors. Only the top layer can be read out with full resolution. Each low layer can only be read out with less than full resolution to generate fewer sensor output values than the total number of pixel sensor locations. Typically, the sensor groups are arranged in cells, each cell including a S sensor groups (e.g., S=4), with S sensors in the top layer and fewer than S sensors in each low layer of the cell. Typically, each cell includes at least one shared sensor (a sensor shared by two or more VCF sensor groups) in each low layer, and each cell includes sensor selection switches (e.g., transistors) between the cell's sensors and a sense node.

Vertical color filter sensor group array with full-resolution top layer and lower-resolution lower layer

A vertical color filter sensor group formed on a substrate (preferably a semiconductor substrate) and including at least two vertically stacked, photosensitive sensors, and an array of such sensor groups. In some embodiments, a carrier-collection element of at least one sensor of the group has substantially larger area, projected in a plane perpendicular to a normal axis defined by a top surface of a top sensor of the group, than does each minimum-sized carrier-collection element of the group. In some embodiments, the array includes at least two sensor groups that share at least one carrier-collection element. Optionally, the sensor group includes at least one filter positioned relative to the sensors such that radiation that has propagated through or reflected from the filter will propagate into at least one sensor of the group.

Vertical color filter sensor group with carrier-collection elements of different size and method for fabricating such a sensor group

A vertical color filter detector group with highlight detector for generating data for a picture element. In one embodiment, the detector group includes three photodiodes each having its own spectral sensitivity and saturation exposure level and a highlight diode having a highlight saturation exposure level. The three photodiodes are located substantially each above or below the others in a semiconductor substrate with the highlight diode in close physical proximity thereto. The four diodes react to light exposure at about the same time as one another. The saturation exposure levels of the three photodiodes are about equal to each other and the highlight saturation exposure level is higher than each of the other three levels. The highlight diode may not be directly exposed to light, but it is close enough to the exposed photodiode region to collect some photoelectrons that are not collected by the three photodiodes.

Vertical color filter detector group with highlight detector

A vertical-color-filter detector disposed in a semiconductor structure comprises a complete-charge-transfer detector comprising semiconductor material doped to a first conductivity type and has a horizontal portion disposed at a first depth in the semiconductor structure substantially below an upper surface thereof and a vertical portion communicating with the upper surface of the semiconductor structure. The complete-charge-transfer detector is disposed within a first charge container forming a potential well around it. The horizontal portion of the complete-charge-transfer detector has a substantially uniform doping density in a substantially horizontal direction and the vertical portion of the complete-charge-transfer detector has a doping density that is a monotonic function of depth and is devoid of potential wells. A first charge-transfer device is disposed substantially at an upper surface of the semiconductor structure and is coupled to the vertical portion of the complete-charge-transfer detector.

Complete-charge-transfer vertical color filter detector

An electronic shutter switching transistor for a CMOS electronic is formed in a semiconductor substrate of a first conductivity type. The transistor comprises a pair of spaced apart doped regions of a second conductivity type opposite the first conductivity type disposed in the semiconductor substrate forming source/drain regions. A gate is disposed above and insulated from the semiconductor substrate and is self aligned with the pair of spaced apart doped regions. A well of the second conductivity type laterally surrounds the pair of spaced apart doped regions and extends deeper into the substrate than the doped regions. A buried layer of the second conductivity type underlies and is in contact with the well.

Electronic shutter using buried layers and active pixel sensor and array employing same

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Woodside, CA, United States of America

Richard B Merrill