Digital Equipment Corporation

Compaq Computer Corporation, Inc.

F5 Networks, Inc.

Richard B Gillett, Jr

Darrel D Donaldson

Douglas D Williams

Simon C Steely, Jr

Glenn P Garvey

Tryggve Fossum

Wayne M Cardoza

Bradley E Cain

H Bruce Butts, Jr

Michael A Berger

James N Leahy

Jonathan C Nicklin

Charles Kaufman

Kathleen D Morse

A primary (e.g., master) file system stores multiple files and corresponding metadata. A view generator function receives template information (e.g., view configuration information) specifying types of metadata information associated with the multiple files stored in the primary file system. Based on processing of the metadata information in the primary file system as specified by the template information, the generator function produces metadata for inclusion in a secondary file system, which is used to satisfy search inquiries associated with the multiple files stored in the primary file system. According to one arrangement, the generator function replicates metadata information in the primary file system as specified by the template information for inclusion in the secondary file system. The secondary file system can include metadata from other sources as well that produced by the generator function. The secondary file system enables more efficient handling of search inquiries than applying search inquiries to the master file system.

File system management with enhanced searchability

A multi-node computer network includes a plurality of nodes coupled together via a data link. Each of the nodes includes a local memory, which further comprises a shared memory. Certain items of data that are to be shared by the nodes are stored in the shared portion of memory. Associated with each of the shared data items is a data structure. When a node sharing data with other nodes in the system seeks to modify the data, it transmits the modifications over the data link to the other nodes in the network. Each update is received in order by each node in the cluster. As part of the last transmission by the modifying node, an acknowledgement request is sent to the receiving nodes in the cluster. Each node that receives the acknowledgment request returns an acknowledgement to the sending node. The returned acknowledgement is written to the data structure associated with the shared data item. If there is an error during the transmission of the message, the receiving node does not transmit an acknowledgement, and the sending node is thereby notified that an error has occurred.

High-performance communication method and apparatus for write-only networks

High performance recoverable communication method and apparatus for

An error recovery method and apparatus has specific application in a networking arrangement having a plurality of individual processing nodes which communicate via shared memory space. For error recovery, the system uses a reliable error count, the value of which is maintained by all of the nodes. When an error is detected, the error count is incremented, and all of the active nodes are provided with the new error count. Any of the nodes can run the error recovery method, and may gain exclusive access to the network by acquiring an error recovery spinlock. Once the spinlock is acquired, the node holding the spinlock increments the error count and confirms that all active nodes have received the new error count. The spinlock is thereafter released.

Method for error recovery spinlock in asymmetrically accessed

An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.

Apparatus and method for intelligent multiple-probe cache allocation

A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one. The inactive counter bank is available for reading by the dedicated BEM processor (23) while the counters of the active counter bank are being incremented. Preferably, each counter bank contains a large number of counters (e.g., 64K), each having a large capacity (e.g., 32 bit). As a result, a large number of different events can be counted over an indefinitely long period of time.

Bus event monitor

A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.

Commander node method and apparatus for assuring adequate access to

A node includes logic circitry for transmitting and receiving data on a backplane bus. The driver in the transmitting logic in the node acts with the current source provided by the bus to decrease the transition time of the data transmitted onto the bus. A coupling resistor is included in the node for individually coupling the driver in the node to the bus for limiting voltage excursions on the bus and providing impedance matching between the node and bus and permitting driver overlap at the bus so that higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized.

Node with coupling resistor for limiting current flow through driver

A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorites, require access to the bus.

Lookahead bus arbitration system with override of conditional access

A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

Method and apparatus for managing multiple lock indicators in a

A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Lockhead bus arbitration system with override of conditional access

A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Node adapted for backplane bus with default control

A system and method for nodes to obtain access to a bus. In this arbitration method, a central arbiter selects a particular node and issues a conditional grant. The conditional grant is transmitted before it is determined whether access to the bus will actually transfer to another node. Each node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When a node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.

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Westford, MA, United States of America

Richard B Gillett, Jr