Bae Systems Information and Electronic Systems Integration Inc.

Richard B Elder, Jr

Steven E Turner

James R Jolly

Lynn M Shepard

Richard A Faust, Iii

Gregory T Griffin

Susan F Lindemann

An emitter ID ambiguity reduction system includes a Mission Data File Ambiguity Resolution matrix that contains both a) the INTEL-based emitter parameters data necessary to break emitter-by-emitter ambiguities, and b) the action(s) the Electronic Warfare (EW) system is to take to collect that data. Control software is triggered via either external command or per Mission Data File information (such as that contained in the Ambiguity Resolution Matrix). The emitter ID ambiguity reduction system includes Data collection hardware and firmware and Data Analysis OFP software algorithm(s).

ID ambiguity reduction

A system and method for adaptive spurious signal (spur) processing at a broadband RF receiver. Spur processing addresses the detection of spurs generated by the receiver when high level RF signals are present at its input. The spurs can lead to undesired false detections. Based on signal parameters of the received RF signal, the system detects a strong enough real signal that would cause a spur and prevent generation of false reports. The adaptive spur mitigation scheme uses multiple detection and report thresholds to enable false report rejection with an improved high probability of rejecting false detections, while minimizing the adverse effects on multi-tone dynamic range. The necessary detection and report thresholds are generated based on a system level behavioral model that predicts the performance of several different types of spurs as a function of signal parameters. The thresholds are tuned to match the behavior of the dominant spur.

Adaptive spur processing

A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

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Bedford, NH, United States of America

Richard B Elder, Jr