Allegro Microsystems, LLC

Sprague Electric Company

Richard B Cooper

Maxim Klebanov

Washington Lamar

Devon Fernandez

Robert J Stoddard

Roger C Peppiette

Harianto Wong

Juin Jei Liou

Yigong Wang

Chung C Kuo

John D Macdougall

Zhixin Wang

Wei Liang

An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

Output driver having reduced electromagnetic susceptibility and associated methods

An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.

Electronic device with adjustable reverse breakdown voltage

In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

Electrostatic discharge protection device

A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Vertical hall effect element with structures to improve sensitivity

A semiconductor integrated circuit has a P-type substrate and a plurality of PN-junction isolated islands of N-type, a first one of the islands may contain a power device which during certain periods of operation causes the first island to become forward biassed and to inject electrons into the substrate. Collection of these injected charges by a second island at one side of the injecting island is reduced by a separate protective bipolar transistor formed in a third N-type island. The third island is preferably interposed between the injecting island and the islands to be protected, but may be located anywhere with respect to the injecting transistor. The emitter of the protective transistor is electrically connected to an N-type portion of the first island. The collector of the protective transistor is connected to the P-type isolation-wall portion of the substrate located between the injecting transistor and the small islands to be protected. The base of the protective transistor, and the isolation-wall portion of the substrate at the opposite side of the first island, are electrically connected to a circuit ground point in the integrated circuit. This causes preferential injection through that part of the forward biassed PN-junction of the injecting island, which part is farthest from the second island. It also generates a field under the first island, proportional to the magnitude of the injected current, that further diverts and prevents diffusion of the injected charges toward the second island.

Separate protective transistor

In an integrated circuit in which a first PN-junction-isolated island may momentarily become forward biased with respect to the surrounding substrate and inject unwanted charge that is collected by second islands adjacent one side of a first island, the injected charge is drawn away from the second islands and to a gatherer-collector island located at another side of the first island. The first island, gatherer-collector island and intervening substrate therebetween serve respectively as the emitter, collector, and base of a protective transistor. This transistor becomes a highly efficient collector of injected charge when the protective-transistor collector is hard wired to ground and the protective-transistor base is hard-wire connected to the substrate portion between the injecting first island and adjacent second island.

Epitaxial island with adjacent asymmetrical structure to reduce

High voltage integrated circuit field plates that are connected directly to the epitaxial pockets over which they lie, are formed simultaneously with high resistivity polysilicon resistors and are insulated from cross-over metal by a dual insulation of silicon dioxide and silicon nitride. Without adding to these process steps, MNS capacitors are formed that have a higher packing density than their MOS counterparts. The space saving MNS capacitors are thus space-wise and process-wise compatible with the polysilicon field plates that occupy much less chip real estate than do diffused channel stops.

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Shrewsbury, MA, United States of America

Richard B Cooper