Mstar Semiconductor, Inc.

Arm Limited

Mstar France Sas

Mstar Software R&d (shenzhen) Ltd.

Mstar Software R&d, Ltd.

Richard Anthony Lane

Cyril Valadon

Simon John Craske

Andrew John Turner

Michael Alexander Kennedy

Mark B Murphy

Francesc Boixadera

Neil Colin Campbell

A data processing system includes an interrupt controller having a priority level arbitrator and trigger circuitry. The priority level arbitrator and the trigger circuitry operate in parallel to process interrupt signals received by an interrupt signal receiver. The trigger circuitry generates a trigger signal initiating interrupt processing before the priority level arbitrator has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

Speculative interrupt signalling

An interrupt controller includes a priority level arbitrator () including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer () for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator () using priority level data associated with the respective interrupt signals.

Interrupt signal arbitration

Techniques are provided for decoding tail-biting convolutional codes by using information within the received data stream that traditionally has not been used or been available to the convolutional decoder, e.g., cyclic redundancy check (CRC) and bit information known by both the transmitter and receiver. Further, a single parallel trace-back is used that reduces implementation complexity. In addition, the least reliable decisions made during forward processing may be reversed in order to generate additional possible codeword candidates. These techniques can be used to reduce false detection rates (FDRs) and/or detection error rates (DERs).

Tail-biting convolutional decoder and decoding method

Techniques are provided for a demodulation and decoding method and apparatus for a given user equipment device to receive a one or more Orthogonal Frequency Division Multiplex (OFDM) symbols over a control channel, where the OFDM symbols comprise a plurality of resource element groups distributed in time and frequency that are combined to form control channel elements. Those resource element groups that form specific control channel elements for the user equipment device and those resource element groups that form common control channel elements for one or more user equipment devices including the given user equipment device are identified. The resource element groups that form the specific control channel elements and the resource element groups that form the common control channel elements are demodulated to generate encoded control messages comprising one or more control channel elements.

Control channel demodulating and decoding method and communication apparatus using the same

A method of steering a channel estimation search window, the method comprising providing a series of raw CIR tap values to span a channel estimation search window containing a sub-window whose contents are intended to be passed for further processing to produce a refined CIR estimate, determining, amongst a plurality of groups of continuous tap values within the window, the group containing the largest amount of signal energy and time-shifting the window as necessary to arrange that the group so determined occupies the sub-window.

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Cambridge, United Kingdom

Richard Anthony Lane