Arm Limited

Richard Andrew Paterson

Rainer Herberholz

Seow Chuan Lim

Peter Andrew Rees Williams

Oded Golombek

Robert John Harrison

Einat Luko

Anitha Kona

Steven Douglas Krueger

Dominic William Brown

Christopher Vincent Severino

Gergely Kiss

Csaba Kelemen

Ramnath Bommu Subbiah Swamy

Peter Uttley

Simon Crossley

Jeffrey Scott Boyer

Alessandro Renzi

Disclosed are methods, systems and devices for storing states in a memory in support of applications residing in a trusted execution environment (TEE). In an implementation, one or more memory devices accessible by a memory controller may be shared between and/or among processes in an untrusted execution environment (UEE) and a TEE.

Method, system and circuit for managing a secure memory partition

An integrated circuit comprises a power input, digital logic circuitry, a plurality of charge stores, and obscuring circuitry. The charge stores are configured to receive power from the power input, are distributed through the digital logic circuitry and are capable of providing power to the digital logic circuitry. The obscuring circuitry is configured to obscure electromagnetic emissions associated with flow of current in current loops between the plurality of charge stores and the digital logic circuitry by switching between a plurality of different charge store activation patterns, wherein each charge store activation pattern describes a different selection of one or more of the plurality of charge stores providing power to the digital logic circuitry at a given time.

Integrated circuit power supply

Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

Method and/or system for testing devices in non-secured environment

An integrated circuit comprises first and second power domains, and a message handling unit to control passing of messages sent from a sender device in the first power domain to a receiver device in the second power domain. The message handling unit writes messages sent from the sender device to a message storage area, provided in the second power domain. The message handling unit is responsive to a message send request from the sender device requesting sending of at least one message to the receiver device when at least one device in the second power domain is in a quiescent state, to transmit a wakeup request to a second domain power controller to request that said at least one device in the second power domain transitions from the quiescent state to an awake state.

Message handling unit

An integrated circuit () has first and second domains (). The first domain has a power controller () to control the power state of at least one device () in the second domain based on power management signals exchanged on a power management channel () between the first and second domains A reset isolation bridge () is provided on the power management channel () between the first and second domains (). The bridge () has first and second interfaces () to exchange the power management signals with the first and second domains respectively. Isolating circuitry () is provided in the bridge () to respond to a reset indication () indicating reset of one of the first and second domains, to isolate state transitions of the power management signals at the first and second interfaces () from each other.

Reset isolation bridge

A method for correlating first and second local time counts in first and second integrated circuits is provided. The first and second integrated circuits communicate via a communication network. A separate time control signal path is also provided between the integrated circuits. The method comprises determining a signal propagation latency associated with propagation of a latency determining signal between the integrated circuits on the time control signal path, and correlating the first and second local time counts in dependence on the signal propagation latency and a time correlating signal transmitted on the time control signal path.

Correlating local time counts of first and second integrated circuits

A data processing apparatusincludes processing circuitryperforming processing operations which move the processing circuitrybetween logical states. Monitoring circuitrymonitors logical state variables of the processing circuitry and these are supplied to prediction circuitrywhich detects predetermined patterns within the logical states which are indicative (previously correlated with) of a future potential temporary insufficiency in the supply power to the processing circuitry. When such a pattern is detected, then power control circuitryserves to trigger a mitigation response to counteract the future potential temporary insufficiency in power supply, such as temporarily reducing the clock frequency and/or boosting the supply voltage.

Apparatus and method for controlling a power supply to processing circuitry to avoid a potential temporary insufficiency in supply of power

Sequential logic elements may consume less static power in response to a first state of a clock signal than in response to a second state of a clock signal (the first and second state may be either low or high depending on the type of sequential logic). This can be exploited to reduce static power consumption of an integrated circuit by controlling the level of a clock signal so that is in the first state for a greater amount of time than the second state.

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Thurgoland, United Kingdom

Richard Andrew Paterson