Cadence Design Systems, Inc.

Richard Allen Woodward, Jr

Randall Scott Lawson

Brett Allen Neal

Ken Wadland

Sean Bergan

Joseph Dexter Smedley

Jelena Radumilo-Franklin

Frank X Farmar

Paul S Musto

Gregory M Horlick

Regis R Colwell

Charles Winston Grant

Walter M Katz

Steve Russo

Edmund J Hickey

Rahil Rajesh Kothari

David Tsai

Wiley Gillmor

Mahmoodreza Jahanseirroodsari

Alan G Strelzoff

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an electronic design and providing, at a graphical user interface, an option to change an object associated with the electronic design. Embodiments may further include identifying a damage area associated with the electronic design, the damage area including an object therein. Embodiments may also include generating a polygon for the damage area and caching one or more voids located outside of the damage area. Embodiments may further include performing a cut and stamp operation on a portion of the electronic design associated with the damage area and populating, at the graphical user interface, a repaired damage area.

System and method for updating shapes associated with an electronic design

The present disclosure relates to a method for routing in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, the electronic circuit design having a plurality of terminal pads associated therewith. Embodiments may further include generating a change in at least one of a size or an existence of at least one of the plurality of terminal pads. Embodiments may also include routing a portion of the electronic design based upon, at least in part, the generated change.

Routing process including dynamically changing pad sizes

The present disclosure relates to a method for visualizing an electronic circuit design. The method may include receiving the electronic circuit design, wherein the electronic circuit design includes at least one timing constraint. The method may also include identifying the at least one timing constraint and displaying, at a graphical user interface associated with the one or more computing devices, the at least one timing constraint and a physical routing associated with the electronic circuit design. The method may further include receiving a user input associated with the electronic circuit design and dynamically updating a graphical representation of the at least one timing constraint, in response to the received user input.

Display process

A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.

Deterministic, parallel execution with overlapping regions

A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Method and system for routing optimally between terminals through intermediate vias in a circuit design

A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.

Method and mechanism for implementing PCB routing

Techniques that can improve the efficiency of routing where connections are subject to elongation constraints. The design can be optimized by estimating elongation needed to meet constraints after an initial routing solution has been generated, but before elongation is actually applied to detailed paths. Paths can be re-routed at this earlier stage if it is determined that too much elongation, or too much elongation in crowded areas, will need to be added after the detail routing stage.

Global constraint optimization

A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.

Growing community of inventors

San Diego, CA, United States of America

Richard Allen Woodward, Jr