International Business Machines Corporation

Isys Technologies, Inc.

Richard Allen Kelley

Danny Marvin Neal

Steven Mark Thurber

Guy L Guthrie

Wen-Tzer Thomas Chen, Jr

Charles B Perkins, Jr

Douglas R Chisholm

John David Wilson

Donall G Bourke

Hartmut R Schwermer

Carl A Malmquist

Richard L Place

John M Nelson

Roy Y Liu

Gregory D Float

David Carroll Challener

Adalberto Guillermo Yanes

Dan Marvin Neal

Richard Alan Dayan

Patrick Allen Buckland

Wan Lin Leung

Paul Lee Clouser

Price Ward Oman

John Mason Elmore

Bruce Leroy Beukema

Ronald Edward Fuhs

Michael Anthony Perez

Thomas Basilio Genduso

James O Nicholson

John Daniel Upton

Palmer E Newman

Joseph Curtis Diepenbrock

Paul Gordon Robertson

James T Moyer

Hartmut Ulland

Donald Ingerman

Lawrence Dean Whitley

Edward Robert Vanderslice

Frank J Pita

Mark C Snedaker

Robert G Iseminger

Robert Andrew Lackman

Kenneth Alan Riek

Guenter Hahn

Padmavathy Tamirisa

Leslie F McDermott

Klaus Muenzner

Melvin Kent Benedict

Carl Raymond Waters

A videoconferencing apparatus and method are implemented. Each participant in the videoconference has a representation within the system as a &ldquo;stick figure,&rdquo; or linear frame, object similar to &ldquo;stick figure&rdquo; objects in the computer animation art. A participant's linear frame object is endowed with the persona of the participant by wrapping the object with an outer texture generated from a preloaded image of the participant. Small tags placed at preselected locations on each participant are detected by the videoconferencing system, and each of the participants stick figures is animated in accordance with changes in positions as revealed by the tags.

Video conferencing apparatus and method therefor

A docking station system for use with a computer system which includes an externally accessible PC Card interface for transferring signals conforming to the PC Card standard to a docking station enclosure. The docking station enclosure includes a PC Card connector that connects to and passes interface signals between the PC Card interface of the computer system and the docking station enclosure. The docking station enclosure further includes an ISA bus structure conforming to the ISA bus standard. Additionally, the docking station enclosure incorporates conversion logic which is connected to receive signals from the computer system via the PC Card connector, and converts these received signals to signals for operating the ISA bus structure. The computer system includes conversion logic which is connected to receive signals from the docking station enclosure via the PC Card connector, and to convert these signals to system interrupt requests. In this manner, one or more ISA adapters can be utilized in the docking station enclosure to emulate one or more PC Card functions at the PC Card interface.

Enabling a docking station for ISA adapters

A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

Transaction credit control for serial I/O systems

A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.

Enhanced bus arbiter utilizing variable priority and fairness

A system and method for optimally processing split request transactions across a PCI-X bridge with a PCI-X bridge buffer. The split transaction mode of the PCI-X bridge buffer is toggled between a No Over-commit mode and an over-commit mode. Over-commitment of the buffer is inhibited when the split transaction mode is toggled to the No Over-commit mode and when the buffer is over committed by the bridge. At least some over-commitment of the buffer is allowed by the bridge when the split transaction mode is toggled to the over-commit mode and when the buffer is not over committed by the bridge. The over-commit mode may be an Over-commitment mode or a Flood mode. The Over-commitment mode allows some degree of over commitment of the buffer by the bridge while the Flood mode allows the bridge to forward all split request transactions regardless of size of the transactions or amount of available space in the buffer when the Over-commit mode is in a Flood mode. The split request transaction is controlled and forwarded based on the toggled split transaction mode. The system comprises at least a toggle switch and a control system. The split transaction mode is toggled to or maintained at a particular mode based on whether a retry or disconnect of the split completion transaction by the PCI-X bridge has or has not occurred and whether the buffer is or is not over committed.

Toggle for split transaction mode of PCI-X bridge buffer

The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

Apparatus and method of allowing PCI v1.0 devices to work in PCI v2.0 compliant system

A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Method and system for interrupt handling using device pipelined packet transfers

A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.

System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer

Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

Buffer management for improved PCI-X or PCI bridge performance

A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.

Buffer assignment for bridges

Method and system for interrupt handling using system pipelined packet transfers

A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus. The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the device driver is designed to issue the load request in response to receiving an interrupt or to check status in the device. The source of the interrupt is preferably the target of the load request.

Selectively flushing buffered transactions in a bus bridge

A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.

Method and system for providing hot plug of adapter cards in an expanded slot environment

A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.

Ordering for pipelined read transfers

A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction.

Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging

Growing community of inventors

Apex, NC, United States of America

Richard Allen Kelley