Texas Instruments Corporation

Richard Allen Faust

Jiong-Ping Lu

Imran Khan

Kaiping Liu

Wei-Yung Hsu

Qi-Zhong Hong

Sudtida Lavangkul

Noel M Russell

Young-Joon Park

Jonathan Philip Davis

Qing-Tang Jiang

Robert M Higgins

Kalyan Chakravarthy Cherukuri

Thomas Edward Lillibridge

Andrew Frank Burnett

Li Chen

Anagha Shashishekhar Kulkarni

Joseph Nguyen

Srinivas Raghavan

A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Multiple depth vias in an integrated circuit

Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads with improved reliability due to a sacrificial metal oxide and the methods of making the under bump metallization structures. A barrier layer is formed over a bond pad. A seed layer is formed over the barrier layer. A bump resist pattern is formed exposing an area over the bond pad and a metal layer is electroplated on the seed layer.

Passivation process to prevent TiW corrosion

A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.

Method of fabricating metal-bearing integrated circuit structures having low defect density

A copper interconnect having a transition metal-silicon-nitride barrier (). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (). The copper () is then deposited over the transition metal-silicon-nitride barrier () with good adhesion.

In-situ co-deposition of Si in diffusion barrier material depositions with improved wettability, barrier efficiency, and device reliability

The present invention provides, in one embodiment, An integrated circuit device (). The integrated circuit device () comprises a circuit feature () located over a semiconductor substrate () and an insulating layer () located over the circuit feature (). A protective overcoat () is located over the insulating layer () and a metal structure () is located over the protective overcoat (). The metal structure () is electrically connected to the circuit feature () by an interconnect (). The metal structure () is coated with a conductive encasement (), the conductive encasement () terminating at a perimeter () of the metal structure (). Another embodiment of the invention in a method of manufacturing an integrated circuit device ().

Selectively encased surface metal structures in a semiconductor device

According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Methods for providing improved layer adhesion in a semiconductor device

A method ( ) of fabricating an electronic device ( ) formed on a semiconductor wafer. The method forms a dielectric layer ( ) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes ( ) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer ( ) adjacent at least a portion of the dielectric layer.

Semiconductor device with silicon-carbon-oxygen dielectric having improved metal barrier adhesion and method of forming the device

A copper interconnect having a transition metal-nitride barrier ( ) with a thin metal-silicon-nitride cap ( ). A transition metal-nitride barrier ( ) is formed over the structure. Then the barrier ( ) is annealed in a Si-containing ambient to form a silicon-rich capping layer ( ) at the surface of the barrier ( ). The copper ( ) is then deposited over the silicon-rich capping layer ( ) with good adhesion.

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Dallas, TX, United States of America

Richard Allen Faust