Plessey Semiconductors Limited

Mitel Semiconductor Limited

Zarlink Semiconductor Limited

Richard Albon

David Johnston

Alan Martin

David A Williams

Neil S Hastie

David John Johnston

Martin Alan

A frequency synthesiser comprises a voltage controlled oscillator, VCO, having means for fine tuning the oscillator frequency and switchable capacitive elements for coarse tuning the oscillator frequency. First comparison means are provided for comparing the frequency and phase of the output of the VCO or a signal derived therefrom with that of a reference frequency signal to provide an error signal, the error signal being provided to said means for fine tuning the oscillator frequency. Second comparison means are provided for comparing the error signal against one or more reference values and a control means receives the result of the comparison from the second comparison means and switches said switchable capacitive elements on and off in dependence upon the result so as to coarse tune the oscillator frequency.

Voltage controlled oscillators

A synchronous single port random access memory comprises a core,of memory cells,arranged as rows and columns. The rows are addressed by a row decoder,and the memory cell outputs are connected as columns to a column decoder and multiplexer,The decoder and multiplexer,selects groups of memory cells,from the addressed row and connects these to sense amplifiers,Changes in address are propagated immediately to the core,so that the selected memory cells,are connected as quickly as possible and without any fixed delays to the sense amplifiers,Similarly, a read clock &ldquo;rclk&rdquo; enables the sense amplifiers,immediately upon becoming active.

Synchronous memory

A semiconductor memory, for example of the ROM type, has columns of memory cells with a bitline for each column connected to the cells of the column. The bitlines are connected via multiplexers to the input of a sense amplifier. Before column selection, the bitlines are held uncharged. When a column is selected, its bitline is connected to a charging voltage by a pull up transistor.

Semiconductor memories

In a static random access memory made up of six-transistor memory cells arranged in rows and columns, an arrangement for detecting open circuit or 'soft' defects in the individual inverters of a memory cell includes lowering the supply voltage of a cell under test to overcome the clamping effect of a feedback inverter, applying input signal voltage changes to one of the bit lines associated with the cell, and testing for the expected voltage changes on the other bit line associated with the cell.

Memory defect detection arrangement

A contents addressable memory comprising an array of contents addressable memory cells arranged in rows and columns, each row of the array having a respective case between address bit values of a data word or words to be retrieved from the memory and bit values held by the cells of the respective row, and a chain of cells associated one with each match line to indicate which, if there are more than one, of the match lines indicating a match is of the highest priority.

Contents addressable memory

In a contents addressable memory for a fully associative cache memory in which address bit values in respect of data to be retrieved from cache are applied to the bit lines of respective columns of cells for comparison with the bit values held by the cells, a match in any one cell is arranged to forward bias a match line device in that cell, the match line devices of a row being connected in cascade, so that if a match is obtained along a row a current path is provided along the row to a respective current sensing circuit to indicate the match.

Content addressable memory having match line transistors connected in

A current sensing read arrangement for a static random access memory in which critical nodes in the sensing arrangement are equalised before read-out commences, and in which differential outputs are applied to a gating arrangement which terminates the read-out as soon as a recognisable output signal is obtained, so as to minimise power consumption.

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Tavistock, United Kingdom

Richard Albon