N*able Technologies, Inc.

Fujitsu Corporation

Richard Alan Weiss

Eric A Murray

Mogens Lauritzen

Leonard Scott Veil

Gary Paul Ward

A method and system for secure transactions. The method and system comprise a security co-processor and an interface for interfacing the security co-processor to a host computer system. The method and system wherein secure transaction processing is performed locally in the security co-processor and non-secure transaction processing is performed in the host computer system. The method and system further include means for providing trusted input coupled to the security co-processor. In addition, the method and system include a second interface coupled to the security co-processor for receiving sensitive data from a smart card, and a trusted display coupled to the security co-processor for providing true transaction information. One advantage of the method and system in accordance with the present invention is that transactions are protected from unauthorized intrusion and, in addition, participation is proven so that transactions cannot be repudiated. Another advantage is that the method and system maintain compatibility with smart cards technology. Yet another advantage is that, because the security co-processor has functionality, smart cards require built-in functionality only for storing sensitive data including account number and private-key and for providing digital signatures to prove participation. Moreover, smart cards can carry biometric data to be recognized by the method and system for an even more reliable proof of participation and card-holder verification. With less built-in functionality, the smart cards are less complex and less expensive. Finally, the method and system are easily implemented with current technology, and the overall cost of the system is reduced.

Method and system for secure transactions in a computer system

A system and method for generating a random number is disclosed. The method and system include providing at least one oscillator, providing a sampler, and providing a sample control. The sampler is coupled to the at least one oscillator. The sampler is for sampling the at least one oscillator to provide at least a portion of the random number. The sample control is coupled to the sampler and is for controlling the sampler to sample the at least one oscillator at an interval which is based on a portion of a previous random number provided using the at least one oscillator.

Method and system for providing a random number generator

A microprocessor synchronously executes instructions, the instructions including integer instructions for performing integer operations and floating point instructions for performing real number operations. An instruction pipeline has a plurality of successive stages for synchronously executing each of the instructions in parallel, with integer and floating point instructions being intermixed in the pipeline. Each of the plurality of successive stages simultaneously operates on a different one of the instructions. An integer unit executes the integer instructions and forms an integer result based on an integer operation performed on at least one integer operand or integer result. A floating point unit executes the floating point instructions and forms a floating point result based on one such floating point operation performed on at least one floating point operand or floating point result. A data path is shared by the integer unit and the floating point unit for communicating between the plurality of successive stages in the instruction pipeline integer operands or the integer results and the floating point operands or the floating point results.

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Los Altos Hills, CA, United States of America

Richard Alan Weiss