International Business Machines Corporation

Tandem Computers Incorporated

Richard Alan Vrba

Donavon W Johnson

Nikhil A Mehta

James Stevens Klecka

Louis Michael Hornung

Larry Leonard Lamano

Kyran Wilfred Fey, Jr

William Clyde Cockerill

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

High-performance fault tolerant computer system with clock length

A fault tolerant computer system having a plurality of processor modules having independent clocks for processing an instruction stream, global memory accessible by all of the processor modules, and a local memory configured within each processor module and clocked synchronously therewith. The local memory is periodically refreshed between accesses to the local memory by the processor. Warning signals indicating a potential access to the local memory are provided to a refresh controller and the local memory is refreshed or the refresh is aborted depending upon the number of clock cycles available before a local memory access occurs. A speculative refresh may be stalled until a processor instruction is decoded to determine whether a local memory access is requested or not.

Fault-tolerant computer system with hidden local memory refresh

A memory control structure for a pipe-lined mini-processor which allows the processor to work with relatively slow memories without degradation of performance. The memory structure includes a memory selector which provides an interface between the processor output and the inputs of a plurality of memories of different types and speeds. The memory selector receives address and control information from the processor and generates the timing and selection signals for the memories. The memory structure also includes fan-in circuitry connected to the outputs of all the memories. The fan-in circuitry includes latches for sampling the output of each memory and multiplexing the memory outputs onto a single data bus for transfer of data from the memories to the processor.

Memory control structure for a pipelined mini-processor system

Logic circuitry is provided for controlling the transfer of data between 1) a low cost pipelined processor and its associated memory, 2) between the processor and input/output devices, and 3) between the input/output devices and memory. A plurality of unidirectional busses are provided to interface the processor and memory and a bidirectional buss is provided to interface with the input/output devices. The logic circuitry provides a control function to steer data over the proper buss structures interconnecting the processor, the memory and the input/output devices and provides those interconnections in a manner which allows the processor to overlap input and output functions.

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Austin, TX, United States of America

Richard Alan Vrba