Qualcomm Incorporated

Qualcomm Mems Technologies, Inc.

Richard Alan Stewart

Dexter Tamio Chun

Subrato Kumar De

Franklin Peter Antonio

Matthew Stuart Grob

Gene Wesley Marsh

Jon James Anderson

Bohuslav Rychlik

Brian K Butler

Leonard N Schiff

Unnikrishnan Vadakkanmaruveedu

William G Ames

Gheorghe Calin Cascaval

Vinay Mitter

Ankur Jain

James T Determan

Douglas Grover

Paras S Doshi

Ananthanarayanan Chockalingam

Marie M Bjerede

Arthur S Kerns

Clarence Chui

Ryan Donovan Wells

Yanru Li

Gurvinder Singh Chhabra

Richard Senior

Nieyan Geng

Ali Akbar Merrikh

Roger K Stewart

Jeffrey Hao Chu

Andres Alejandro Oportus Valenzuela

Raghuveer Raghavendra

Douglas H Moe

Christopher L Platt

Hans Lee Yeager

Robert S Hastings

Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

System memory latency compensation

This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

Dynamic mapping of applications on NVRAM/DRAM hybrid memory

Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.

Bandwidth-monitored frequency hopping within a selected DRAM operating point

Aspects include computing devices, systems, and methods for managing a first computing device component of a computing device in order to extend an operating life of the computing device component. In an aspect, a processing device may determine a condition estimator of the first computing device component, determine whether the condition estimator of the first computing device component indicates that a condition of the first computing device component is worse than the condition of a second computing device component, and assign workloads to the first and second computing device components to balance deterioration of the condition of the first and second computing device components in response to determining that the condition estimator of the first computing device component indicates that the condition of the first computing device component is worse than the condition of the second computing device component.

Runtime optimization of multi-core system designs for increased operating life and maximized performance

Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

Transaction elimination using metadata

Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

System and method for allocating memory to dissimilar memory devices using quality of service

Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

Systems and methods for providing error code detection using non-power-of-two flash cell mapping

Aspects include computing devices, systems, and methods for implementing executing decompression of a compressed page. A computing device may determine a decompression block belonging to a compressed page that contains a code instruction requested in a memory access request. Decompression blocks, other than the decompression block containing the requested code instruction, may be selected for decompression based on their locality with respect to the decompression block containing the requested code instruction. Decompression blocks not identified for decompression may be substituted for a fault or exception code. The computing device may decompress decompression blocks identified for decompression, terminating the decompression of the compressed page upon filling all blocks with decompressed blocks, faults, or exception code. The remaining decompression blocks belonging to the compressed page may be decompressed after or concurrently with the execution of the requested code instruction.

Efficient decompression locality system for demand paging

Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system to increase operating life and maximize device performance by wear-leveling the processor cores. A reliability engine may be configured to collect operation or built in self test data of thermal output and current leakage, and historical operation time for a group of equivalent processor cores configured for the same purpose. Collected data may be applied to a weighted function to determine priorities for each equivalent processor core in the group. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores. A high level operating system may issue a process request specifying a processor core and the specified processor core may be translated to a different processor core according to the order of processor cores dictated by the priorities.

Various embodiments of methods and systems for thermal energy management in a portable computing device ('PCD') based on power level calculations are disclosed. An exemplary method includes tracking instantaneous operating temperatures and active power supply levels to one or more components. With an estimate or measurement of ambient temperature, the instantaneous operating temperature values and active power supply level values can be used to calculate an instantaneous thermal resistance value. In the event that thermal energy generation should be managed, a target operating temperature may be used with the ambient temperature and the instantaneous thermal resistance value to solve for an optimum power supply level. The active power supply level may then be adjusted based on the calculated optimum power supply level.

System and method for thermal management in a portable computing device using thermal resistance values to predict optimum power levels

Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

System and method for dynamically allocating memory in a memory subsystem having asymmetric memory components

Various embodiments of methods and systems for managing battery capacity in a portable computing device ('PCD') are disclosed. One such method includes leveraging a request/grant algorithm that receives a request from an offline component to come online. If battery capacity is available to accommodate the offline component, the request is granted. If battery capacity is not available to accommodate the offline component, the request is authorized at a reduced power level or capacity is created by reducing power to online components. Another method polls a battery to monitor demand on its capacity by active components. Offline components likely to come online concurrently with the active components are identified and ranked based on power consumption. A target current margin is adjusted based on the highest power consumption associated with an identified block of offline components.

System and method for dynamic battery current load management in a portable computing device

Growing community of inventors

San Diego, CA, United States of America

Richard Alan Stewart