Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Richard Alan Krzyzkowski

Guy Harlan Humphrey

Brian C Miller

Gayvin E Stong

David Lawrence Linam

Paul Douglas Nuber

Jason Todd Gentry

William Scott Burton

Dan Stotz

Laurent F Pinot

Edgardo Pablo Lopez

M Jason Welch

Kristin Marie Richling

A computer system performs a verification process that quickly and efficiently determines a temperature rise of DC conductor lines of an IC design caused by Joule heating in nearby AC conductor lines of the IC design, and whether the temperature rise is acceptable in terms of an electromigration performance of the IC design.

Computer system and method for determining a temperature rise in direct current (DC) lines caused by joule heating of nearby alternating current (AC) lines

A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor. The processor is configured by the software to: read a defined location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; read a defined number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; test electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes within the subset is equal, and change properties within the integrated circuit if the clock signal traversal time is not equal; and add the logical blocks to each of the interconnect routes within the subset, wherein each of the logical blocks is connected to the open end of one of the interconnect routes within the subset.

System and method for simplifying clock construction and analysis

A technique for preventing high current shorts through I/O pads of an integrated circuit during power up and power down is presented. In accordance with the invention, the voltage levels of the core power supply that powers the internal circuitry of the integrated circuit and the I/O power supply that powers the input and/or output pad drivers is monitored to detect the condition wherein the core power supply is powered down and the I/O power supply is powered up. Upon detection of this condition, the pad drivers are disabled, preferably by disabling the pre-drivers that generate the pre-drive signals that drive the output driver devices. In a preferred embodiment, the process/voltage/temperature adjustment circuitry is leveraged to disable the output pads during power up and down.

Method for reducing short circuit current during power up and power down for high voltage pad drivers with analog slew rate control

Insertion delay associated with receiving and distributing a clock within an IC is removed using a DLL. The structure of a differential receiver in the feedback circuit of the DLL is substantially matched to the structure of an input differential receiver which receives and inputs a differential input clock into the DLL. In this manner, the insertion delay associated with the input differential receiver is removed from a delay-corrected clock output from the DLL. By substantially matching one or more aspects of the feedback circuit to one or more aspects of a clock distribution circuit for distributing the delay-corrected clock, the insertion delay associated with the clock distribution circuit can also be removed from the delay-corrected clock.

Method and apparatus for distributing clocks

A high gain, low input capacitance clock buffer includes a plurality of transistors configured to supply an inverted representation of an input reference signal by alternatively switching to provide the output. While either of the transistors is operating to switch the input clock signal, the other transistor is in a stable state. Furthermore, by using n-type FET's, significant power reduction and space savings may be achieved.

Circuit and method for a high gain, low input capacitance clock buffer

A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.

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Fort Collins, CO, United States of America

Richard Alan Krzyzkowski