Motorola Corporation

Richard A Wheelus

Kenneth W Jones

Robert Han Wu

Todd D Haverkos

Jerome A Gerner

Content testing (302-306) and comparator testing (312-326) of a tag section (24, 26) of a cache tag memory array is performed to confirm that the tag section (24, 26) is functional. For content testing (302-306), each tag location is tested once. Comparator testing (312-326) is performed to determine the functionality of the comparator (240, 260) of the cache tag memory array. The number of tests performed for the comparator testing is 2.times.M+2, where M is the number of bit positions in the tag location. Two of the tests are for testing the comparator's ability to identify correctly hits within the tag section (312-316). The other tests are for testing the comparator's ability to identify correctly misses within the tag section at each bit position of the tag locations (322-326).

Method of testing a cache tag memory array

An integrated circuit memory (140) includes programmable fuses (20) coupled to scannable flip-flops (25). The programmable fuses (20) and scannable flip-flops (25) are implemented in a scan chain, and are used to program specific information about the integrated circuit memory (140), such as for example, repair (redundancy) information, wafer lot number and wafer number, die position on the wafer, or any other information that would be useful during or after package testing.

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Austin, TX, United States of America

Richard A Wheelus