Brocade Communications Systems, Inc.

Auspex Systems, Inc.

Richard A Walter

L Vincent M Isip

Subhojit Roy

Naveen Maveli

Cirillo Lino Costantino

Clive M Philbrick

Peter K Craft

David A Higgen

Dennis Hideo Makishima

Daniel Y Chung

Daniel Ji Yong Park Chung

Shahe Hagop Krakirian

Paul Lester Popelka

Carlos Alonso

Edward John Row

Lakshman Narayanaswamy

Tarun Kumar Tripathy

Stephen D Elstad

Daniel Murray Jones

Leslie Thomas McCutcheon

Amod Prabhakar Bodas

Donald Wayne Sterk

Murali Sundaramoorthy Repakula

Paul Brian Del Fante

Michael Yiu-Wing Pong

Subbaro Arumilli

The capability to encrypt or compress the traffic over network links, thus improving the security of the link on the performance of the links, and the capability to encrypt/decrypt data stored on the storage devices without requiring specialized hosts or storage devices. In a first embodiment, traffic to be routed over a selected link needing encryption and/or compression is routed to hardware which performs the encryption and/or compression and returned for transmission over the link. A complementary unit at the second end of the link routes the received frames to complementary hardware to perform the decryption and/or decompression. The recovered frames are then routed to the target device in a normal fashion. In a variation of this first embodiment the hardware is developed using an FPGA. This allows simple selection of the desired feature or features present in the switch. The switch can be easily configured to perform encryption, compression or both, allowing great flexibility to a system administrator. In a second embodiment frames can be encrypted by a switch and then provided to the storage device in this encrypted manner. The frames from the storage device are decrypted before provision to the requesting host. By performing the encryption and decryption in the switch, conventional hosts and storage devices can be utilized.

Method and apparatus for compression of data on storage units using devices inside a storage area network fabric

Method and apparatus for encryption of data on storage units using devices inside a storage area network fabric

Method and apparatus for encryption or compression devices inside a storage area network fabric

Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch. In an alternative embodiment, specialized hardware scans incoming frames and detects the virtualized frames which need to be redirected. The redirection is then handled by translation of the frame header information by hardware table-based logic and the translated frames are then returned to the fabric. Handling of frames not in the table and setup of hardware tables is done by an onboard CPU.

Host bus adaptor-based virtualization switch

Hardware-based translating virtualization switch

A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks. Upon receiving requests for data from the NP, the FSP checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request. The resulting scalable computer provides higher data availability, faster access to shared data, and reduced administrative costs via data consolidation.

Processing system with dynamically allocatable buffer memory

Growing community of inventors

San Jose, CA, United States of America

Richard A Walter