International Business Machines Corporation

Other

Richard A Swetz

Peter H Hochschild

Carl Alfred Bender

Alan G Gara

Martin Ohmacht

Thomas M Gooding

Ashutosh Misra

Jay Robert Herring

Monty Montague Denneau

Rudolf Adriaan Haring

Kevin J Gildea

Don Darrell Reed

Henry Stanley Warren, Jr

Fu Chung Chang

Denis R Gallagher

Dong Chen

Paul William Coteus

Todd Edward Takken

Mark Edwin Giampapa

Mark Gregory Megerian

Rama Krishna Govindaraju

Mark James Jeanson

Gerard M Salem

Gerard Vincent Kopcsay

Paul Gregory Crumley

Matthew Roger Ellavsky

Thomas A Liebsch

Ralph E Bellofatto

Daniel J Littrell

Brandon Edward Schenck

Ben Jesse Nathanson

Singpui Zee

Rama J Govindaraju

Ross L Franke

There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated 'pre-counter' while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the 'sweeper' state machine accesses the pre-counter.

RAM based implementation for scalable, reliable high speed event counters

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Global synchronization of parallel processors using clock pulse width modulation

In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Efficient probabilistic duplicate packet detector in computer networks

An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Power throttling of collections of computing elements

There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

Methods for routing packets on a linear array of processors

There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.

System for independently transferring data using two independently

A segregated waste disposal device is disclosed which includes a plurality of waste receptacles provided in a main housing, each of the plurality of waste receptacles receiving one of a plurality of distinct waste products, respectively, including glass and metal. An opening within the main housing receives at least one of the glass and metal waste, and the weighted lid connected to the main housing crushes waste deposited into the opening. The lid may be opened either by hydraulic or mechanical spring mechanisms and a grate member provided within the opening and beneath the weighted lid allows crushed glass to free-fall therethrough into a predetermined receptacle. A sweep arm sweeps remaining crushed waste off of the grate into a waste receptacle other than a waste receptacle containing crushed glass.

Environmental non-powered pail type trash container

A segregated waste disposal system is disclosed which includes a plurality of separate bins for receiving paper, plastics, glass, and metal respectively. Two openings are provided within the overall unit, one of the openings receiving paper/plastics, the other opening receiving glass/metal. The respective openings perform different disposal functions with respect to the materials inserted therein, whereby the glass/metals opening compresses the glass/metals such that the compressed glass will immediately fall through a grate into a glass bin and a sweep arm sweeps compressed metal to an adjacent metals bin. The paper/plastics opening compresses the paper/plastic and subsequently shreds the compressed material. Deflection to a respective paper/plastics bin is determined by an operators instruction achieved via a selection panel provided in connection with the waste disposal system.

Segregated waste disposal system

Growing community of inventors

Mount Kisco, NY, United States of America

Richard A Swetz