Honeywell Information Systems Inc.

Richard A Slater

Joseph L Ryan

Richard R Watkins

John P Stafford

Frederick E Kobs

Steven G Taibbi

Odas P Plank

A logic memory addressing system requiring minimal central processing unit (CPU) control is provided for extending the memory addressing capacity of a CPU. A logic control system simplistic in design and including a logic decoding unit responds to control words issued by the CPU by way of control and address busses to randomly access memory words, and to effect the exchange of information between the memory unit and a data bus.

Random access memory system for extending the memory addressing capacity

A logic control system in a video display terminal is disclosed for synchronizing the operation of dual, asynchronously operating CRT control unit semiconductor chips to accommodate a substantially increased number of visual attributes per display row with minimal effect on data character transfer rates.

Dual CRT control unit synchronization system

Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

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Nashua, NH, United States of America

Richard A Slater