Advanced Micro Devices Corporation

Legerity, Inc.

Richard A Relph

David A Kaplan

Denise Kerstein

Govind Kizhepat

Philip Simmons

Jeremy W Powell

A security module in a memory access path of a processor of a processing system protects secure information by verifying the contents of memory pages as they transition between one or more virtual machines (VMs) executing at the processor and a hypervisor that provides an interface between the VMs and the processing system's hardware. The security module of the processor is employed to monitor memory pages as they transition between one or more VMs and a hypervisor so that memory pages that have been altered by a hypervisor or other VM cannot be returned to the VM from which they were transitioned.

Monitoring of memory page transitions between a hypervisor and a virtual machine

A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word. A data steering means is arranged between the PCI bus and the write or read buffer to connect required pins of the PCI interface with a required location in the buffer.

Variable 16 or 32 bit PCI interface which supports steering and swapping of data

An analog delay line uses an analog-to-digital (A/D) converter which converts an analog signal into a plurality of digital signals. Digital delay lines, each including a series of digital delay elements, delay the respective digital signals. A digital-to-analog (D/A) converter converts the digital signals back into a delayed analog signal.

Analog delay line implemented with a digital delay line technique

The invention provides a system and a method for managing digital data in a computer peripheral device which receives the data from a host computer. The system includes a processing circuit which receives data from the host and uses the data to control the computer peripheral device. The system further includes a memory device which stores data and comprises a plurality of storage locations. The system still further includes a memory management unit for controlling the storage of data in the memory device. The system still further includes a compression program for effecting compressed storage of data in memory. The memory management unit determines when the amount of data stored in the memory device exceeds a predetermined threshold and generates a compression signal. The compression program responds to the compression signal by effecting compressed storage of data. In the preferred embodiment of the present invention, the plurality of storage locations comprising the memory device is arranged in ordered arrays of subsets of storage locations. The memory management unit determines when the amount of data stored in one particular subset of the ordered array of subsets exceeds a predetermined threshold and generates a compression signal.

System and method for using a memory management unit to reduce memory

A circuit and method for clocking for logic circuits use delay line techniques to time the clock signal. The inputs into a logic circuit are associated with a validity signal, which is delayed by a delay line for at least the propagation delay of the logic circuit. The delayed validity signal is used to latch an output signal produced by the logic circuit in response to the inputs.

Self-clocked logic circuit and methodology

A programmable delay line has delay elements that are responsive to at least one of two different calibration signals for varying their drive power characteristics and hence the delay period. Preferably, there are two sets of delay elements, responsive to a respective calibration signal, with one set comprising much fewer delay elements than the other set. The delay elements may be responsive to a digital calibration signal for discrete control, an analog calibration signal for continuous control, or both.

Programmable delay line

A floating point timer comprises a floating point counter using a reference clock signal generated by a digital ring oscillator having an oscillation period that matches the delay of the worst case path through the floating point counter. The digital ring oscillator utilizes a digital delay line which repeatedly delays a bit for the oscillation period and feedback logic to reapply the delayed bit for another oscillation. The digital delay line includes enough high-precision digital delay elements whereby the oscillation period is at least as great as that of the delay of the worst case path through the floating point counter.

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Austin, TX, United States of America

Richard A Relph