Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Richard A Pedersen

Robert Leonard Pritchett

John A Carelli, Jr

Jack Kane

James E Morehouse

An integrated circuit includes first and second field effect transistors having differing channel lengths, and a means for comparing the channel currents flowing therethrough. An excessive difference of currents indicates 'short channel' effects, which can degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.

Integrated circuit with channel length indicator

A detector circuit (102) is connected to the gate of a thyristor (103) for generating an output signal indicating the presence of current flowing out of the cathode of the thyristor. A switch circuit (101), which is responsive to a control signal, selectively applies the control signal in a first state to the gate and, when the control signal is in a second state, connects the detector circuit to the gate to detect current flowing out of the gate of the thyristor.

Detector circuit for thyristors

A silicon semiconductor integrated logic circuit of the injection or merged transistor logic type has output contacts in which ohmic and Schottky barrier portions are combined. A portion of the surface region of each output transistor collector is converted to more heavily doped N-type conductivity so that a metal contact applied thereto makes low resistance contact to the more heavily doped portions but forms a contact of the Schottky barrier type to the more lightly doped portion. The effect of the Schottky contact portion is to control minority carrier storage in the collector of the NPN output transistor by forcing the hole excess density at the Schottky portion surface to be zero thereby enabling short propagation delay time.

Combined ohmic and Schottky output transistors for logic circuit

A logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration. The circuit has favorable switching speed and power dissipation characteristics and reduces the effect of both capacitive loading and series resistance in signal interconnections. An efficient layout of one such logic circuit has intercell wiring channels formed across the circuit and has the inputs and outputs of the circuit arranged in two lines each of which crosses perpendicular to the wiring channels.

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New Tripoli, PA, United States of America

Richard A Pedersen