International Business Machines Corporation

Richard A Neuner

Gerald H Miracle

Peter L Potvin

John R Flanagan

Daniel Francis Casper

Lee Hardy Wilson

James T Moyer

Frank J Janniello

Vahe A Minassian

Maurice E Carey

In a data processing system in which an extender unit interconnects the parallel bus of a control unit and a serial link of an extender channel, the channel and the extender unit send and receive serial frames that permit the extender unit to operate under the protocol of the parallel bus with either byte mode devices or non-byte mode devices. The control unit can be modified to operate with a byte mode device in data streaming, a high speed data transfer mode.

Method and apparatus for supporting byte-mode devices and non-byte-mode

Method and apparatus for making wavelength and power adjustments to a laser in a wavelength division multiplex system includes an extender card containing fiber optic transmission devices and path attenuators is inserted in the system in place of a card containing the laser to be adjusted. The extender card includes switches to put the laser under adjustment in known states for making power adjustments and wavelength adjustments without affecting system operation. After adjustments have been made, the extender card is removed and the laser card is reinstalled in the system.

Method and apparatus for making wavelength adjustments in a wavelength

A device control unit operating under the protocol of a parallel bus is connected by a serial link to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit interconnects the parallel bus and the serial link and performs the specific operations of the parallel bus protocol. The channel and the extender unit send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features. New operations using the protocol reduce the delays that would otherwise be required in the communications between the channel and the extender unit. The serial link can be made longer when the delays are reduced.

Apparatus for communication between a device control unit having a

An asynchronous high-speed data interface for coupling a serial channel to a parallel control unit. A first state machine, running synchronously with the channel transmitter clock, controls the filling of a pair of dual-port input buffers in alternating fashion with frame contents bytes from incoming serial frames that have been deserialized and decoded. A second state machine, running synchronously with a second clock that is asynchronous with the channel transmitter clock, controls the transfer of the frame contents bytes from the selected input buffer to one of a pair of output buffers en route to the control unit. Upon detecting the receipt of the third incoming frame contents byte, the first state machine sets a start latch, causing the second state machine to begin transferring data from the selected input buffer to the selected output buffer while the input buffer is still being filled. Means are provided for disregarding the frame contents bytes that have been transferred to the selected output buffer if the frame is ultimately aborted.

Serial frame processing system in which validation and transfer of a

A system for bit character synchronization of an 8/10 bit code being deserialized is provided by a deserializer with a skip bit function input used to move a character boundary one bit at a time, and 8/10 code error detector, a zero disparity character detector and skip pulse generator. After character sychronism is lost, the skip pulse generator is permitted to generate a skip pulse if the following sequence occurs: all bits of the old character boundary have been flushed through the logic circuits, at least one non-zero disparity character has been detected, and an 8/10 code error is detected. After character synchronism is re-acquired, then the skip pulse generator is no longer permitted to generate a skip pulse.

Growing community of inventors

Port Ewen, NY, United States of America

Richard A Neuner