Semicoa Semiconductors

Vram Technologies, LLC

Integrated Discrete Devices, LLC

Luminous Intent, Inc.

Other

Semicoa

Richard A Metzler

Vladimir Rodov

Alexander O Goushcha

Mark Kalatsky

Eddie Bartley

Chris Hicks

Dan Tulbure

Frederick A Flitsch

Field effect semiconductor diodes and improved processing techniques for forming the field effect semiconductor diodes having semiconductor layers forming a source, a body and a drain of a field effect device, the semiconductor layers forming pedestals having an insulating layer and a gate on sides thereof vertically spanning the body and a part of the source and drain layers, and a conductive contact layer over the pedestals making electrical contact with the drain and the gate, the conductive layer being in contact with the body at least one position on each pedestal. The conductive layer may be in contact with the body through at least one opening in the source layer, or the source layer may be a discontinuous doped layer, the body layer extending between the discontinuous doped layer forming the source layer to be in electrical contact with the conductive layer. Other aspects and variations of the invention are disclosed.

Field effect semiconductor diodes and processing techniques

Ultra thin back-illuminated photodiode array fabrication methods providing backside contact by diffused regions extending through the array substrate. In accordance with the methods, a matrix is diffused into one surface of a substrate, and at a later stage of the substrate processing, the substrate is reduced in thickness and a similar matrix is diffused into the substrate from the other side, this second diffusion being aligned with the first and contacting the first within the substrate. These two contacting matrices provide good electrical contact to a conductive diffusion on the backside for a low resistance contact to the backside. Various embodiments are disclosed.

Ultra thin back-illuminated photodiode array fabrication methods

Fast silicon diodes and arrays with high quantum efficiency built on dielectrically isolated wafers. A waveguide is formed in the top surface of the silicon that utilizes total internal reflection from the Si&#x2014;Si Oxide interface to form an internal mirror. This mirror reflects incoming light into the waveguide cavity, with the light being trapped there by surrounding reflective interfaces. A masking layer may be used to define an input window. Individual diodes or linear arrays may be formed as desired. Some alternate embodiments are described.

Fast Si diodes and arrays with high quantum efficiency built on dielectrically isolated wafers

Ultra thin back-illuminated photodiode array structures and fabrication methods. The photodiode arrays are back illuminated photodiode arrays having a substrate of a first conductivity type having first and second surfaces, the second surface having a layer of the first conductivity type having a greater conductivity than the substrate. The arrays also have a matrix of regions of a first conductivity type of a higher conductivity than the substrate extending from the first surface of the substrate to the layer of the first conductivity type having a greater conductivity than the substrate, a plurality of regions of the second conductivity type interspersed within the matrix of regions of the first conductivity type and not extending to the layer of the first conductivity type on the second surface of the substrate, and a plurality of contacts on the first surface for making electrical contact to the matrix of regions of the first conductivity type and the plurality of regions of the second conductivity type.

Fabrication methods for ultra thin back-illuminated photodiode array

A technique, for drawing power from the external signal circuit to power on-chip elements for an integrated circuit diode (ICD), utilizes an integrated diode and capacitor. The capacitor is charged by the external applied voltage during the time the ICD blocks the external current flow. The charged capacitor then acts as a battery to power the on-chip circuits to provide active control for the ICD function. This ICD could be provided as a two terminal discrete diode, or integrated onto a larger IC. This same technique can be utilized for a 'self powered' MOSFET IC (ICM), utilizing a low power logic signal to trigger an internal circuit which would provide a much larger gate drive than the logic signal could provide. This could also be provided as discrete three terminal components, or integrated into a larger IC.

On chip power supply

Trench MOSFETs and self aligned processes for fabricating trench MOSFETs. These processes produce a higher density of trenches per unit area than can be obtained using prior art masking techniques. The invention self aligns all processing steps (implants, etches, depositions, etc.) to a single mask, thus reducing the pitch of the trenches by the added distances required for multiple masking photolithographic tolerances. The invention also places the source regions and contacts within the side walls of the trenches, thus eliminating the lateral dimensions required, for masking and source depositions or implants from the top surface, from the pitch of the trenches. Various embodiments are disclosed.

MOSFET power transistors and methods

Methods and apparatus of forming a semiconductor device using pedestals and sidewalls. The pedestals and sidewalls may provide an etch stop and/or a diffusion barrier during manufacture of a semiconductor device. Processes of forming diode connected vertical cylindrical field effect devices are disclosed to exemplify the use of the pedestals and/or sidewalls. A system for forming the pedestals and sidewalls is described.

Sidewalls as semiconductor etch stop and diffusion barrier

Ultra thin back-illuminated photodiode array structures and fabrication methods

A process of forming fine repetitive geometries using a mask having large mask dimensions. The pitch of the masking pattern on the mask is divided by the process to obtain a smaller pitch in the fine repetitive geometries. At least two working materials are used one of which can be etched without etching a substrate. In one embodiment the two working materials and the substrate are each etched independently. In other embodiments, the substrate and one working material have similar etch rates while the other material is etched independently. Pedestals are formed having an initial pitch. First sidewalls are formed around the pedestals. The pedestals are removed and a second and third sidewall are formed on the inside and outside surfaces of the first sidewall having spaces there-between. The first sidewall is removed generating another space between the second and third sidewall. The spaces and the widths of the second and third sidewalls form final pitches substantially smaller than the initial pitch of the pedestals. The process can be used in semiconductor manufacturing processes as well as other fields. Various geometric shapes for patterning by the method are disclosed.

Method and apparatus for patterning fine dimensions

Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Vertical junction field effect semiconductor diodes

The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

Vertical metal oxide silicon field effect semiconductor diodes

Semiconductor diodes are diode connected cylindrical junction field effect devices having one diode terminal as the common connection between a top gate, a back gate and a first channel terminal of the cylindrical junction field effect devices. The second diode terminal of the semiconductor diodes being the second channel terminal of the diode connected cylindrical junction field effect devices. The method of processing the cylindrical junction field effect devices provide very short channels, shallow diffused regions and trench terminated junctions at the edges of the active device for low forward voltage turn-on and high reverse bias breakdown. The trench terminated junctions spread the breakdown energy over the entire active device region rather than just device edges.

Method and apparatus for cylindrical semiconductor diodes

Semiconductor diodes are diode connected cylindrical field effect transistors having one diode terminal as the common connection between the gate and the drain of the cylindrical field effect transistors. The method of processing the field effect transistor provides very short channels, shallow diffused regions and trench terminated junctions at the edges of the active device. The trench terminated junctions are formed out of a vertical etch cut through the P-N junction at the edge of the device forming the trench which is then passivated with a dielectric material to provide a region of higher breakdown voltage at the edge of the device than is seen within the active device area. The trench terminated junction results in spreading the breakdown energy over the entire active device region rather than just device edges. The preferred fabrication technique for the active device uses two masks and two masking steps, without any critical mask alignment requirements.

Semiconductor diodes having low forward conduction voltage drop, low reverse current leakage, and high avalanche energy capability

Batch thin film capacitors and their methods of manufacture using semiconductor manufacturing techniques. A mask, photo mask or shadow mask, having a pattern is used to form a matrix of rows and columns of thin film capacitors in a wafer. Capacitor terminals are formed in a batch process by separation at column saw areas, depositing a conductive layer and vertically etching horizontal layers of the conductive layer. Capacitance of an individual batch processed thin film capacitor is increased by stacking wafers together prior to separation at the column saw areas and forming capacitor terminals thereafter to couple parallel thin film capacitors together.

Method and apparatus for batch processed capacitors using masking techniques

A bipolar transistor designed to support a substantially uniform current density in base and collector regions to prevent the characteristic early fall-off of bipolar transistor current gain, and to improve the forward safe operating area performance. The advantages of the present invention are achieved by optimally spacing the neighboring emitters in relation to base thickness and further by maintaining a symmetrical topology by the self-aligned formation of emitters and base contacts. The spacing distance between the neighboring emitters does not exceed the base thickness. As a result, the current density below each emitter island is substantially uniform and the transistor as a whole can conduct a higher total current. Moreover, the transistor inhibits formation of current filaments and hot spots because the electric field in the collector region is uniform.

Growing community of inventors

Mission Viejo, CA, United States of America

Richard A Metzler