Delco Electronics Corporation

Gm Global Technolgoy Operations, Inc.

Other

Delphi Technologies, Inc.

Richard A Kennedy

Gregory J Manlove

Jeffrey J Marrah

Seyed R Zarabadi

Myron Glen Padgett

Fred Jay Anderson

Fredrick A Aldridge

Mark A Kady

Stephen L Inman

John R Pacourek

Marvin G Stang

Linh Ngoc Pham

Paul K Bowers

David W Osburn

Thomas Gerard Block

Michael John Easterwood

Richard A Summe

Detlef Griessman

Rohail Andrew Pervez

Matthew James Yarosz

Barry F Koch

Eldred H Wiechmann

Richard I Kunkle

Timothy G Murray

Martin G Gravenstein

A phase compensation circuit, for use with an FM reception system, includes a delay circuit and a control circuit. The delay circuit receives a composite input signal that exhibits a variable phase error and provides a plurality of selectable discrete delays. The control circuit is coupled to the delay circuit and receives a control signal whose value corresponds to the phase error associated with the composite input signal. The control circuit selects one of the plurality of selectable discrete delays responsive to the control signal, which is utilized to delay the composite input signal to provide a phase compensated composite output signal.

Phase compensation circuit

An FM stereo receiving system and a method for aligning phases of RF signals received by multiple antennas. The FM stereo receiving system includes two antennas for receiving RF signals having a common frequency but potentially different phases. The system also includes an FM receiver having a detector output and a pilot output on which a pilot tone, such as a 19 kHz pilot tone, is present. A summer is included in the system for summing the RF signals and providing the summed signal to the receiver. The amplitude modulator of the system resides between one of the antennas and the summer to amplitude modulate the antenna's RF signal at a perturbation frequency which is a whole number multiple greater than 1 of the pilot tone. The receiver thus produces on its phase detector output a phase signal having a frequency equal to the perturbation frequency and a magnitude corresponding to the phase error between the RF signals which is connected in a feedback loop to align the phases.

Diversity receiver for FM stereo utilizing a pilot tone multiple for

A method for tuning and aligning an electronically tuned FM broadcast receiver is described. The system described compensates for the mismatch of component values between the antenna and RF amplifier tuned circuits, and the IF offset between the local oscillator frequency and the center frequencies of the antenna and RF resonant circuits by developing independent tuning signals for the circuits. The system also provides temperature compensation, and can be aligned without mechanically adjusting inductors and/or capacitors in the tuned circuits.

Method and apparatus for tuning and aligning an FM receiver

A radio apparatus with a phase locked loop is disclosed. The apparatus contains a phase detector with first and second inputs, where the first input receiving a reference frequency signal and the second input receives a controllable frequency signal that is controlled by a tuning voltage. Also included is, a loop filter for filtering the output of the phase detector, circuitry for decoding when a phase difference at the inputs of the phase detector exceeds a predetermined value, and a filter bypass circuit. This circuit bypasses operation of the loop filter when the difference at the inputs of the phase detector exceeds a predetermined value, allowing fast voltage changes of the tuning voltage, and providing a short lock time for the phase locked loop.

Fast locking phase locked loop frequency synthesizer

An AM stereo receiver in which a synchronous in-phase signal is determined comprises a low pass filter circuit for determining an average DC value of the synchronous in-phase signal, a reference voltage supply for providing a reference voltage indicative of a predetermined portion of the DC value of the synchronous in-phase signal occurring during a 100% IF signal level condition, a comparison circuit for comparing the average DC value of the synchronous in-phase signal to the predetermined reference, and an output circuit outputting a signal indicative of an out-of-lock condition when the average DC value of the synchronous in-phase signal falls below the predetermined reference.

Out-of-lock detector for synchronous AM detection

An AM stereo input signal is processed by an envelope detector, an in-phase detector and a quadrature phase detector to yield outputs which may carry short noise impulses. Each output is low pass filtered to derive an average signal level and each output is ratiometrically compared to the corresponding average to detect a tic or modulation substantially above the average. In response to a tic a hold circuit generates a flag for a period which depends on the quality of the input signal. A dual mode deemphasis and sample/hold circuit normally filters the audio signal in each channel and is effective for the duration of the flag to hold the existing signal in the circuit to blank out the noise impulse.

Noise blanking circuit for AM stero

An adaptive audio processor for stereo AM broadcast signals includes independent signal processing paths. Each path has a variable lowpass filter and a matrix and variable Q 10 kHz notch filter to form LEFT and RIGHT channel signals with a 10 kHz notched pass band determined by adjacent channel noise. A 10 kHz pass band signal representative of adjacent channel noise from one of the signal processing paths is compared to a reference to generate a correction signal that is fedback to control the lowpass and notch filters. The correction signal adjusts the pass band and Q of the lowpass and notch filters so that the effects of adjacent channel noise are minimized. Other receiver signals which are reflective of the quality of the received broadcast signal, e.g., the AGC signal, an excess modulation signal, and a receiver microprocessor signal are similarly employed to control the lowpass and notch filters.

Adaptive audio processor for AM stereo signals

A Stop On Station (SOS) circuit for a AM and FM radio receivers evaluates field strength of a received station signal and in addition measures and evaluates the frequency of the IF signal so as to assure that the received signal is essentially centered at the IF frequency to identify candidate stations signals which are suitable for listening. The IF frequency for a received candidate station signal is evaluated for an evaluation period of time (e.g., for 40 milliseconds). During each 40 millisecond period, fifteen samples of the frequency of the IF signal are counted and evaluated. If the frequency of the measured signal falls within acceptable limits, a four stage binary persistence counter is incriminated. If a count of 12 or more out of the 15 possible counts is accumulated therein during a 40 ms evaluation period, a station signal is considered to be suitable from a standpoint of received frequency and a 'frequency pass' signal is generated. The SOS circuit, in turn, generates a 'Stop' signal if the AGC signal is above a predetermined threshold at the time the pass signal occurs. In this case of FM signals, the magnitude of ultrasonic noise (noise in the range of 100 kHz to 200 kHz) in the output of the FM detector is measured and used to identify acceptable station signals. Noise above a threshold value eliminates a station signal from consideration.

Stop on station circuit including center channel detector

A differential operational amplifier comprises a differential input circuit that provides a differential output signal to a plurality of independent output circuits. The gains of the differential input circuit and one output circuit are set by a fixed bias source. A variable bias source controlled by an external signal determines the gain of each other output circuit so that various attenuation characteristics are obtained in the other output circuits without affecting the operating conditions of the operational amplifier. A feedback element between the output of the one output circuit and the differential input circuit assures gain stability.

Multiple output operational amplifier

An ajustable switched capacitor circuit comprises a first stage, a second stage and a switched capacitor circuit coupling the output of the first stage to the input of the second stage. The operating parameters of the second stage are a function of the effective resistance of the switched capacitor coupling circuit. An attenuator interposed between the output of the first stage and the input of the switched capacitor coupling circuit controls the charging voltage of the switched capacitor coupler thereby controlling its effective resistance and parameters of the output stage. The signal loss through the attenuator is continuously adjustable responsive to an external control voltage to obtain continuous control of various output stage parameters. The output stage may comprise a filter having the parameters of its transfer function determined by the effective resistance of the switched capacitor coupling circuit.

Switched capacitor filters with continuous time control

An audio detector circuit forms L+R and L-R audio signals from an intermediate frequency compatible quadrature amplitude modulated signal in the form (1+L+R)cos(fct+.phi.) where .phi. contains phase modulated L+R and L-R signals. An envelope detector generates an L+R audio signal and in-phase and quadrature phase detectors produce L+R and L-R audio signals, respectively. The difference between L+R outputs of the envelope and in-phase detectors are amplified to generate a cosine correction signal. Each detector includes a differential operational amplifier having an field effect feedback transistor coupled between each amplifier output and the corresponding input and an field effect transistor coupling the compatible quadrature amplitude modulated signal to the operational amplifier inputs. The impedances presented by the feedback transistor are varied by the cosine correction signal to remove the cosine component of the compatible quadrature amplitude modulated signal while frequency multiplication at the IF frequency rate provides the correct phase audio signal for matrix and noise processing.

Compatible quadrature amplitude modulation detector system

A Phase Locked Loop (PLL) circuit includes a control signal generator, a digital phase detector, logic gates, a charge pump (charge/discharge circuit), a transmission gate, a loop filter, a lead-lag filter and a voltage controlled oscillator (VCO). Outputs of the digital phase detector are coupled through the logic gates to inputs of the charge pump. An output of the charge pump is coupled to the capacitor and to a first input/output of the transmission gate. A second input/output of the transmission gate is coupled to an input of the loop filter whose output is coupled to an input of the VCO whose output is coupled to a first input of the digital phase detector. A second input of the digital phase detector is coupled to a source of a reference frequency signal. The control signal generator generates non-overlapping complementary control signals with one of same connected to the logic gates and the other connected to the transmission gate. Accordingly, the electrical path from the digital phase detector to the charge pump through the logic gates is closed and the electrical path from the capacitor to the loop filter is open or vice versa. The loop filter includes an operational amplifier with AC feedback which is controlled by the same signal which controls the logic gates. The PLL circuit is typically formed on a single integrated circuit silicon chip using CMOS technology.

Phase locked loop circuit with digital control

An FM stereo radio circuit has an ultrasonic noise detector and an amplitude noise detector each for detecting impulse noise by developing an average noise signal and comparing the average noise signal with an attenuated value of the instantaneous noise signal to generate a noise flag. A dual mode circuit normally operates as a low pass filter for a deemphasis function and is switched by the noise flag to operate as a sample and hold circuit which blanks the noise pulse. The dual mode circuit uses a switched capacitance design and is driven by clock signals to serve as a filter. The clock signals are stopped by the noise flag to effect the sample and hold function.

Combined deemphasis circuit and noise blanker

An integrated circuit FM detector which compensates for variations in semiconductor manufacturing process and temperature employs a pair of serially connected switched capacitor-operational amplifier combinations. The first combination is a frequency to voltage converter which uses a switched capacitor input circuit which is clocked at the frequency of the input signal, an operational amplifier and a feedback resistor. The second combination is a compensation circuit which uses an input resistor, a feedback switched capacitor circuit and an operational amplifier. The feedback switched capacitor circuit is clocked at a fixed rate. Reversal of the roles of the resistor and the switched capacitor in the first and second combinations compensates for both temperature and manufacturing process variations. The electrical separation of the input and feedback switched capacitor circuits helps to insure against the generation of unwanted noise in the form of beat frequencies which could be generated if the switched capacitor circuits were used as the input and feedback circuits of a single operational amplifier.

FM detector using switched capacitor circuits

An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

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Russiaville, IN, United States of America

Richard A Kennedy