Digital Equipment Corporation

Richard A Gahan

Tadhg Creedon

Eugene G O'Neill

Fearghal Morgan

Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.

Multi-level round robin arbitration system

A data processing system comprising a main memory 10 with a 32-bit longword data bus 11 and an address bus 12, and a link unit 20 using 16-bit shortwords. The link unit has two shortword memories 26 and 28 for descriptor and message shortwords. Descriptor shortwords are exchange individually with the memory 10, residing in the lower halves of longword locations; message shortwords are exchanged with the memory 10 through a concatenation and deconcatenation unit 40 so that they are stored in pairs in longword locations. Unit 20 passes descriptor addresses (with top bit 1) from a register 25 and message addresses (with top bit 0) from a register 27 to the main memory through address processing means 36, which comprises a multiplexer 43 with its two data inputs fed with two versions of the address with a 1-bit shift between them. The top address bit controls the multiplexer, so that the main memory address steps by 1 for every step of a descriptor address or every second step of a message word address.

Data processing unit for transferring data between devices supporting

A logic circuit for use as an arbiter to arbitrate among N devices of a computer system for access to a shared resource. The arbiter generates state variables to represent arbitration win information. The state variables are generated through the use of request for arbitration signals input to the arbiter, present values of the state variables and internally generated intermediate arbitration win signals to provide a cost effective, efficient implementation of the logic required for the arbitration in a smaller physical solution for the arbitration logic.

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County Galway, Ireland

Richard A Gahan