Energy Conversion Devices, Inc.

Alphasil Incorporated

Raf Electronics

Other

Honeywell G.m.b.h.

Burroughs, Inc.

Mosaic Systems, Inc.

Richard A Flasck

Scott H Holmberg

Stanford R Ovshinsky

Herbert Stopper

Benny Irwin

Howard K Rockstad

Thomas D Stahl

Principles of nonimaging optics, imaging optics, etendue matching, and the Constant Brightness Theorem are used to provide an ultra-efficient solid state lighting optical system for stage and theatrical profile spotlights. Used in combination, an array of high brightness light emitting diodes, a nonimaging optical transform element, and an image forming optical element enable the design of profile spotlights capable of high brightness, low electrical power consumption, sharp gobo imaging, adjustable beam intensity profiles, and use of current industry standard accessories and elements, such as gobos, blades and irises.

High efficiency hybrid illumination system

A wafer based active matrix reflective light encoding system formed on a conventional wafer including a specular reflective back surface and an LC or similar characteristic material formed thereon which is electronically altered to impart or encode information onto a light beam which is directed to and reflected therefrom. The LC material preferably is a solid light modulating material having bodies of LC material suspended in the solid material. The matrix transistors can be any conventional type of crystalline based structure, such as NMOS, CMOS, or PMOS and can be coupled to the bit and/or word lines by fuses to prevent shorts associated with a single pixel from shorting a whole line. The pixel capacitor can include a junction or oxide type capacitor or a combination thereof. The matrix bit and/or word lines can include strapping to prevent open lines. The wafer based active matrix can be mated to a light directing and projecting structure to form a reflective image plane module which projects the reflected beam for viewing or imaging, such as through one or more lens to form a part of a projection system.

Wafer based active matrix

An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Method of manufacturing flat panel backplanes, display transistors

An improved active matrix reflective projection system utilizing a conventional wafer includes a reflective image plane module forming two focal images. The image plane module includes light directing and reflecting structures and a wafer based active matrix. A source of light is directed to the image plane module active matrix from a first image plane. The active matrix imparts information onto a light beam reflected therefrom. The image plane module projects the reflected beam for viewing, such as through one or more lens. The active matrix reflective projection system can be a monochrome projector including a single reflective image plane module or can be a full color system including three reflective image plane modules. Each color image plane module operates on a single color component, red, green or blue, which then are combined on a screen or before projecting on the screen to form the full color projection image. The active matrix includes a specular reflective back surface and an LC or similar type material formed thereon which is electronically altered to impart the information to the light beam reflected therefrom. The image plane module includes a mirror or mirror portion which directs the light or light component to the wafer based active matrix which reflects an encoded light beam therefrom and which projects the reflected light to be viewed.

Active matrix reflective image plane module and projection system

Liquid crystal screen for overhead projector

A reflective image plane module including light directing and reflecting structures and a wafer based active matrix mated thereto. A source of light is directed to the reflective image plane module wherein the wafer based active matrix imparts or encodes information onto a light beam reflected therefrom. The reflective image plane module projects the reflected beam for imaging or viewing, such as through one or more lens. The reflective image plane module includes a prism or mirror which passes the light or light component through a first surface to the wafer based active matrix mated to a second surface and which projects the reflected light from the first surface to be viewed or imaged. The wafer based active matrix includes a specular reflective back surface and an LC or similar type material formed thereon which is electronically altered to impart the information to the light beam reflected therefrom. The reflective image plane module can be utilized in various light encoding systems such as a monochrome projector including a single reflective image plane module or a full color system including three reflective image plane modules, one for each color, which then are combined on a screen or before projecting on the screem to form the full color projection image.

Reflective image plane module

An active matrix reflective projection system utilizing a conventional wafer includes a reflective image plane module. The reflective image plane module includes light directing and reflecting structures and a wafer based active matrix mated thereto. A source of light is directed to the reflective image plane module wherein the wafer based active matrix imparts information onto a light beam reflected therefrom. The reflective image plane module projects the reflected beam for viewing, such as through one or more lens. The active matrix reflective projection system can be a monochrome projector including a single reflective image plane module or can be a full color system including three reflective image plane modules. Each color reflective image plane module operates on a single color component, red, green or blue, which then are combined on a screen or before projecting on the screen to form the full color projection image. The wafer based active matrix includes a specular reflective back surface and an LC or similar type material formed thereon which is electronically altered to impart the information to the light beam reflected therefrom. The LC material preferably is a solid light modulating material having bodies of LC material suspended in the solid material. The reflective image plane module includes a prism or mirror which passes the light or light component through a first surface to the wafer based active matrix mated to a second surface and which projects the reflected light from the first surface to be viewed.

Active matrix reflective projection system

LCD screen illumination is provided by a neon tube formed to fit closely adjacent the screen. A tube formed to fit around the periphery of the screen shielded from the viewer's eyes can be utilized to front light the screen. A serpentine shaped tube can be placed adjacent the back of the screen to back light the screen. The tube can be formed to have a size coextensive with the screen configuration and can have a light diffuser between the tube and the screen to provide uniform illumination. The tube can provide any desired color, an adjustable high maximum surface brightness, high electrical efficiency and a narrow profile.

Method of illuminating flat panel displays to provide CRT appearing

Subdivided pixels are provided with interconnected and hence redundant row and column bus lines to reduce fatal defects. The respective redundant row and column lines also can be interconnected between subpixels to further reduce defects. One defective subpixel is generally an acceptable non-fatal defect, since the rest of the subpixels are still operative. The subpixels also can be formed with common row and column bus lines. The pixels or subpixels can be connected in a serial serpentine pattern to test all row or all column bus lines at once. After testing, the serial connections are broken.

Method of manufacturing flat panel backplanes including improved testing

Method of manufacturing flat panel backplanes, display transistors and

An improved method of manufacturing thin film transistors. A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor. To reduce shorts and capacitance between the gate and the source or the drain, a dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

Method of manufacturing thin film transistors and transistors made

A programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and substantially non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 20 volts or less, a current of 25 milliamps or less, for 1000 microseconds or less. The cells in the conductive state have a resistance of 500 ohms or less. The cells have a maximum permittable processing temperature of 200.degree. centigrade or more and a storage temperature of 175.degree. centigrade or more. The cells can be formed from chalcogenide elements, such as germanium tellurium and selenium or combination thereof. The cells also can be formed from tetrahedral elements, such as silicon, germanium and carbon or combinations thereof. Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Programmable cell for use in programmable electronic arrays

An improved method of manufacturing thin film transistors. A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

An improved programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The cells have a highly non-conductive state settable and non-resettable into a highly conductive state. The cells have a resistance of 10,000 ohms or more in the non-conductive state which are settable into the conductive state by a threshold voltage of 10 volts or less, a current of 25 milliamps or less, for 100 microseconds or less. The cells in the conductive state have a resistance of 100 ohms or less. The cells have a maximum permittable processing temperature of 400.degree. centigrade or more and a storage temperature of 175.degree. centigrade or more. The cells are formed from doped silicon alloys including at least hydrogen and/or fluorine and contain from about 0.1 to 5 percent dopant. The cells can be plasma deposited from silane or silicon tetrafluoride and hydrogen with 20 to 150,000 ppm of dopant. Each cell in an array is a thin film deposited cell and includes an isolating device which can be a bipolar or MOS device or can be a thin film diode or transistor. The associated addressing circuitry also can be conventional bipolar or MOS devices or thin film deposited devices. The cells have a cell area of less than one square mil to provide a high cell packing density.

Disclosed is a wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.

Growing community of inventors

San Ramon, CA, United States of America

Richard A Flasck