Honeywell Information Systems Inc.

Microcom Systems, Inc.

Hewlett-Packard Development Company, L.p.

Richard A Carey

Jerry Falk

Dennis Kloc

Michael F Onorato

Lewis A Bergins

Roy Greene

An improved system for the transmission of data over a cellular telephone channel is provided. The system is especially adapted to reduce the cost associated with cellular telephone calls by allowing data transmission only when the channel signal level is greater than a pre-defined value, so as maximize the probability that a transmission will be successful. In addition, the system provides for user transparent reconnection and reestablishment of a dropped link, allowing transmission to continue where dropped without the need to retransmit data already successfully received. As an additional benefit, the system provides a mechanism for call timing and billing so that an estimated bill may be generated based on connection time.

Transmission of data over a radio frequency channel

A telecommunications system intermittently checks and, if necessary, adjusts the power level of the transmitted data as a function of the transmission characteristics of the transmission line so as to optimize transmission performance.

Method and apparatus for effecting efficient transmission of data

An interactive terminal computer system is disclosed having a system bus for communicating between elements of the computer system which has apparatus for permitting the execution of a maximum number of concurrent bus cycles without interference with each other.

Apparatus for maximizing bus utilization

An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer system elements and assigns time slots for use of the system bus by arbitrating among various resources competing for access to the bus.

Bus arbitration logic

An interactive terminal includes a central processor unit (CPU) having a microprocessor and a random access memory (RAM). Signals from the microprocessor place the RAM in a write protect mode. If the RAM receives a write instruction from the microprocessor when the RAM is in the write protect mode, then an illegal condition is indicated and a nonmaskable interrupt is generated to allow the terminal to recover. When the RAM is in the write protect mode, signals from the microprocessor restore the RAM to its normal read/write mode.

Write protected memory

An address bus of a central processor unit (CPU) is tested by generating repetitive 'no operation' (NO OP) instructions. A microprocessor in the CPU receives the NO OP instruction code set manually into switches and generates sequential addresses on successive CPU cycles on the address bus. The microprocessor generates a read signal during each CPU cycle which is jumpered to portions of the logic to allow continuity of operation during test.

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Ashland, MA, United States of America

Richard A Carey