Bitmicro Networks, Inc.

Bitmicro LLC

Richard A Cantong

Rolando H Bruce

Marizonne Operio Fuentes

Bharadwaj Pudipeddi

Federico Sambilay, Jr

Joevanni Parairo

In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA. In yet another embodiment of the invention, an article of manufacture comprises a non-transitory computer-readable medium having stored thereon instructions operable to permit an apparatus to perform a method comprising: triggering, by the apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image, wherein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.

FPGA functionality mode switch-over

The present invention relates to an apparatus, method, and/or sequence that adaptively provide the recovery of data after a power cycle sequence, wherein only minimal updates are provided for control blocks associated with the data.

Adaptive power cycle sequences for data recovery

Growing community of inventors

Cabuyao Laguna, Philippines

Richard A Cantong