Micron Technology Incorporated

Intel Corporation

Stmicroelectronics S.r.l.

Rich Fackenthal

Aswin Thiruvengadam

William A Melton

Andrew Oen

Ferdinando Bedeschi

Sean Stephen Eilert

Ravi Prakash Gutala

Nicholas T Hendrickson

Duane R Mills

Reed Linde

Enzo M Donze

Anthony Suk Ko

Sunil Gupta

Peter Leung

Meenatchi Jagasivmani

Chin-Tin Tina Yu

A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value.

Set pulse for phase change memory programming

A memory device and method for programming the memory device, more particularly a single pulse algorithm for programming a phase change memory cell or array. The single pulse can heat the memory cell to above its melting point and reduce in signal level so that the memory cell is crystallized.

In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.

Accelerating phase change memory writes

Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Write performance of phase change memory using set-pulse shaping

A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.

Protection register for a non-volatile memory

Data structures of different sizes may be stored in memory using different ECC schemes. A memory device may include multiple ECC engines to support error correction operations on different sized data structures.

Method, system, and apparatus for ECC protection of small data structures

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

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Carmichael, CA, United States of America

Rich Fackenthal