Atmel Corporation

Riccardo Riva Reggiori

Fabio Tassan Caser

Lorenzo Bedarida

Stefano Sivero

Giorgio Oddone

Simone Bartoli

Andrea Sacco

Massimiliano Frulio

Mirella Marsella

Monica Marziani

Luca Figini

A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers.

Embedded architecture with serial interface for testing flash memories

A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.

Flexible OTP sector protection architecture for flash memories

An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.

Column decoding architecture for flash memories

A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.

System and method for avoiding offset in and reducing the footprint of a non-volatile memory

A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node is configured to receive a charge. A first transistor has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.

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Segrate, Italy

Riccardo Riva Reggiori