Micron Technology Incorporated

Other

Riccardo Muzzetto

Ferdinando Bedeschi

Umberto Di Vincenzo

Daniele Vimercati

Christophe Laurent

Christophe Vincent Antoine Laurent

Graziano Mirichigni

Huy Thanh Vo

Hyun Yoo Lee

Efrem Bolandrina

Suryanarayana B Tatapudi

Marco Sforzin

Corrado Villa

Angelo Visconti

Hari Giduturi

Jeffrey Edward Koelling

Nevil N Gajera

Christian Caillat

Francesco Mastroianni

Michele Maria Venturini

Methods, systems, and devices for balanced codewords for reducing a selected state in memory cells are described. A memory device may divide a sequence of data bits into sets of bits associated with different bit-positions in a coding scheme. The memory device may then balance a first codeword that includes the first set of the data bits in the binary domain to reach a target ratio of logic values for the codeword. Using the first codeword and the other set(s) of data bits, the memory device may balance the remaining two states in the state domain to reach an overall target distribution of the three states. The memory device may then generate one or more codeword(s) for the other set(s) of data bits so that the memory device can write all of the codewords to ternary cells.

Balanced codewords for reducing a selected state in memory cells

The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.

Memory device having an improved ECC architecture

Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

Performing sense operations in memory

The present disclosure relates to operating an array of memory cells, including storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, in which a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.

Methods and systems for improving ECC operation of memories

Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

Read operations based on a dynamic reference

The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.

ECC configuration in memories

Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

Memory cell read operation techniques

The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.

Balancing data in memory

The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ECC correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. The payload is stored in at least part of the parity cells which are not selected to store parity data. Related memory devices and systems are also herein disclosed.

Methods and systems for managing memory with dynamic ECC protection

The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

Unbalanced programmed data states in memory

Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

Decoder architecture for memory device

The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

Providing multiple error correction code protection levels in memory

A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.

Methods and systems for improving read and write of memory cells

The present disclosure relates to a memory device comprising an array of memory cells arranged in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels. Related memory systems and methods are also disclosed.

Architecture for multideck memory arrays

The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

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Arcore, Italy

Riccardo Muzzetto