Stmicroelectronics S.a.

Stmicroelectronics (Grenoble 2) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics (Grenoble) Sas

Riccardo Locatelli

Marcello Coppola

Giuseppe Maruccia

Michael Soulie

Lorenzo Pieralisi

Giuseppe Guarnaccia

Raffaele Guarrasi

Valerio Catalano

Luca Fanucci

Antonio-Marcello Coppola

Daniele Mangano

Sergio Saponara

Cristina Silvano

Francesco Giotta

Philippe Teninge

Franscesco Vitullo

Leandro Fiorin

Gianluca Palermo

Dario Zandri

Nicola L'Insalata

Jose Flich Cardo

Jose Francisco Duato Marin

Jose Cano Reyes

Tony Bacchillone

Antonio-Marcello Coppolla

Esa Petri

Hajer Ferjani

Francesco Vitullo

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Method and apparatus for supporting the use of interleaved memory regions

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

Method and apparatus for use with different memory maps

A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

Method and apparatus for supporting reprogramming or reconfiguring

Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.

Method of data transmission in a system on chip

A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Zero-cycle router for networks on-chip

A switch includes at least one input configured to receive data and at least two outputs configured to send data to at least two further switches in a network via at least two output links. Each output link has a known hop value. The switch further includes a direction determinator that determines a routing direction for the data from information identifying a relative location of the switch in the network and information identifying a destination of said data. A distributor within the switch processes the routing direction and direction information about each output link in order to select one of said at least two outputs for outputting said data. The selection that is made prioritizes output links for selection which have relatively higher known hop values.

Switches and a network of switches

A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.

Method for transferring data from a source target to a destination target, and corresponding network interface

A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.

Programmable data protection device, secure programming manager system and process for controlling access to an interconnect network for an integrated circuit

This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: The control data and the actual data to be transferred are stored in separate first and second memory means.

Buffering architecture for packet injection and extraction in on-chip networks

A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

System for transmitting data within a network between nodes of the network and flow control process for transmitting the data

A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link

A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.

On-chip bandwidth allocator

A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure. Processing circuitry is distributed within the N routers and the N network interfaces for determining direction of the data packet to be transmitted over a path from a source element to a destination element in the ring structure, and for determining at each router in the path which virtual channel is to be used to avoid deadlocks in the transmission.

On-chip packet-switched communication system

A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Growing community of inventors

Grenoble, France

Riccardo Locatelli