Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Stmicroelectronics (Grenoble 2) Sas

Stmicroelectronics (Rousset) Sas

Riccardo Gemelli

Om Ranjan

Denis Dutey

Abhishek Gupta

Nicola Marinelli

Ranjan Om

A method, includes: storing at least one set of data in a memory space, wherein the at least one set of data stored has a memory footprint in the memory space; and coupling, to the at least one set of data, a respective counter indicative of the at least one set of data, wherein the respective counter is embedded in the at least one set of data without increasing the memory footprint in the memory space.

Functional safety method, system, and corresponding computer program product

A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

Functional safety method, corresponding system-on-chip, device and vehicle

Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)

A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

Growing community of inventors

Carugate, Italy

Riccardo Gemelli